When a rule is inserted into a matcher, we search for the suitable
action template. If such template is not found, action template array
is extended with the new template. However, when several threads are
performing this in parallel, there is a race - we can end up with
extending the action templates array with the same template.
This patch is doing the following:
- refactor the code to find action template index in rule create and
update, have the common code in an auxiliary function
- after locking all the queues, check again if the action template
array still needs to be extended
Signed-off-by: Vlad Dogaru <vdogaru@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1746992290-568936-9-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Currently the counter that counts number of rules in a matcher is
increased only when rule insertion is completed. In a multi-threaded
usecase this can lead to a scenario that many rules can be in process
of insertion in the same matcher, while none of them has completed
the insertion and the rule counter is not updated. This results in
a rule insertion failure for many of them at first attempt, which
leads to all of them requiring rehash and requiring locking of all
the queue locks.
This patch fixes the case by increasing the rule counter in the
beginning of insertion process and decreasing in case of any failure.
Signed-off-by: Vlad Dogaru <vdogaru@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1746992290-568936-8-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Rules are inserted into hash table in accordance with their hash index.
When a certain number of rules is reached, the table is rehashed:
a bigger new table is allocated and all the rules are moved there.
But sometimes a new rule can't be inserted into the hash table
because its index is full, even though the number of rules in the
table is well below the threshold. The hash function is not perfect,
so such cases are not rare. When that happens, we want to do the same
rehash, in order to increase the table size and lower the probability
for such cases.
This patch fixes the usecase where rule insertion was failing, but
rehash couldn't be initiated due to low number of rules: it adds flag
that denotes that rehash is required, even if the number of rules in
the table is below the rehash threshold.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1746992290-568936-7-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This patch adds support for Complex Matchers/Rules
Overview:
--------
A matcher can match on a certain set of match parameters. However, the
number and size of match params for a single matcher are limited: all
the parameters must fit within a single definer.
A common example of this limitation is IPv6 address matching, where
matching both source and destination IPs requires more bits than a
single definer can support.
SW Steering addresses this limitation by chaining multiple Steering
Table Entries (STEs) within the same matcher, where each STE matches
on a subset of the parameters.
In HW Steering, such chaining is not possible — the matcher's STEs
are managed in a hash table, and a single definer is used to calculate
the hash index for STEs.
To address this limitation in HW Steering, we introduce Complex
Matchers, which consist of two chained matchers. This allows matching
on twice as many parameters. Complex Matchers are filled with Complex
Rules — rules that are split into two parts and inserted into their
respective matchers.
The first half of the Complex Matcher is a regular matcher and points
to the second half, which is an Isolated Matcher. An Isolated Matcher
has its own isolated table and is accessible only by traffic coming
from the first half of the Complex Matcher.
This splitting of matchers/rules into multiple parts is transparent to
users. It is hidden under the BWC HWS API. It becomes visible only when
dumping steering debug information, where the Complex Matcher appears
as two separate matchers: one in the user-created table and another
in its isolated table.
Some implementation details:
---------------------------
All user actions are performed on the second part of the rules only.
The first part handles matching and applies two actions: modify header
(set metadata, see details below) and go-to-table (directing traffic to
the isolated table containing the isolated matcher).
Rule updates (updating rule actions) are applied to the second part of
the rule since user-provided actions are not executed in the first
matcher.
We use REG_C_6 metadata register to set and match on unique per-rule
tag (see details below).
Splitting rules into two parts introduces new challenges:
1. Invalid Combinations
Consider two rules with different matching values:
- Rule 1: A+B
- Rule 2: C+D
Let's split the rules into two parts as follows:
|---| |---|
| A | | B |
|---| --> |---|
| C | | D |
|---| |---|
Splitting these rules results in invalid combinations like A+D
and C+B.
To resolve this, we assign unique tags to each rule on the first
matcher and match these tags on the second matcher (the tag is
implemented through modify_hdr action that sets value to metadata
register REG_C_6):
|----------| |---------|
| A | | B, TagA |
| action: | | |
| set TagA | | |
|----------| --> |---------|
| C | | D, TagB |
| action: | | |
| set TagB | | |
|----------| |---------|
2. Duplicated Entries:
Consider two rules with overlapping values:
- Rule 1: A+B
- Rule 2: A+D
Let's split the rules into two parts as follows:
|---| |---|
| A | | B |
|---| --> |---|
| | | D |
|---| |---|
This leads to the duplicated entries on the first matcher, which HWS
doesn't allow: subsequent delete of either of the rules will delete
the only entry in the first matcher, leaving the remaining rule
broken.
To address this, we use a reference count for entries in the first
matcher and delete STEs only when their refcount reaches zero.
Both challenges are resolved by having a per-matcher data structure
(implemented with rhashtable) that manages refcounts for the first part
of the rules and holds unique tags (managed via IDA) for these rules to
set and to match on the second matcher.
Limitations:
-----------
We utilize metadata register REG_C_6 in this implementation, so its
usage anywhere along the steering of the flow that might include the
need for Complex Matcher is prohibited.
The number and size of match parameters remain limited — now it is
constrained by what can be represented by two definers instead of one.
This architectural limitation arises from the structure of Complex
Matchers. If future requirements demand more parameters,
Complex Matchers can be extended beyond two matchers.
Additionally, there is an implementation limit of 32 match parameters
per rule (disregarding parameter size). This limit can be lifted if
needed.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1746992290-568936-6-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
In preparation for complex matcher support, introduce the isolated
matcher.
Isolated matcher is a matcher that has its own isolated table.
It is used as the second half of the complex matcher: when the rule
is split into two parts (complex rule), then matching on the first
part will send the packet to the isolated matcher that will try to
match on the second part. In case of miss, the packet goes back to
the matcher's end flow table.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1746992290-568936-5-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
In preparation for complex matcher, expose the function that is
polling queue for completion (mlx5hws_bwc_queue_poll) in header
file, so that it will be used by complex matcher code.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1746992290-568936-4-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
In preparation for complex matcher support, add function for
converting definer fname to str, which will be used in following
patches.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1746992290-568936-3-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
In preparation for complex matcher support, make function
mlx5hws_table_ft_set_next_ft() non-static and expose it in header.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1746992290-568936-2-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
There's a few issues with this function, mainly:
* This function -probably- should have been unsafe from the start. Pointers
are not always necessarily valid, but you want a function that does
field-projection for a pointer that can travel outside of the original
struct to be unsafe, at least if I understand properly.
* *mut Self is not terribly useful in this context, the majority of uses of
from_gem_obj() grab a *mut Self and then immediately convert it into a
&'a Self. It also goes against the ffi conventions we've set in the rest
of the kernel thus far.
* from_gem_obj() also doesn't follow the naming conventions in the rest of
the DRM bindings at the moment, as_ref() would be a better name.
So, let's:
* Make from_gem_obj() unsafe
* Convert it to return &'a Self
* Rename it to as_ref()
* Update all call locations
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Link: https://lore.kernel.org/r/20250513221046.903358-3-lyude@redhat.com
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
There is usually not much of a reason to use a raw pointer in a data
struct, so move this to NonNull instead.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Link: https://lore.kernel.org/r/20250513221046.903358-2-lyude@redhat.com
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
pmem.c regs.c mbox.c identifiers were missing. Add them to
memory-devices.rst following their respective DOC comment includes.
Two acpi.c identifiers were available, but not used in kernel-doc's:
1) Add add_cxl_resources to memory-devices.rst and fix up the Sphinx
complaint on the ascii art by escaping it.
2) Add cxl_acpi_evaluate_qtg_dsm to access-coordinates.rst.
core/features.c is new. Add a "DOC: cxl features" comment to the
source and identifiers to memory_devices.rst.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250513215813.1419645-1-alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Refactor the driver suspend and resume to handle Google GS101 EINT GPIO
pin banks and add the alive pin bank for that SoC.
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Merge tag 'samsung-pinctrl-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v6.16
Refactor the driver suspend and resume to handle Google GS101 EINT GPIO
pin banks and add the alive pin bank for that SoC.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These tests:
"SOCK_STREAM ioctl(SIOCOUTQ) 0 unsent bytes"
"SOCK_SEQPACKET ioctl(SIOCOUTQ) 0 unsent bytes"
output: "Unexpected 'SIOCOUTQ' value, expected 0, got 64 (CLIENT)".
They test that the SIOCOUTQ ioctl reports 0 unsent bytes after the data
have been received by the other side. However, sometimes there is a delay
in updating this "unsent bytes" counter, and the test fails even though
the counter properly goes to 0 several milliseconds later.
The delay occurs in the kernel because the used buffer notification
callback virtio_vsock_tx_done(), called upon receipt of the data by the
other side, doesn't update the counter itself. It delegates that to
a kernel thread (via vsock->tx_work). Sometimes that thread is delayed
more than the test expects.
Change the test to poll SIOCOUTQ until it returns 0 or a timeout occurs.
Signed-off-by: Konstantin Shkolnyy <kshk@linux.ibm.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Fixes: 18ee44ce97 ("test/vsock: add ioctl unsent bytes test")
Link: https://patch.msgid.link/20250507151456.2577061-1-kshk@linux.ibm.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Since commit ce6cb8113c ("tools: ynl-gen: individually free previous
values on double set"), specifying the "multi-attr" property raises an
error unless the "nested-attributes" property is specified as well:
File "tools/net/ynl/./pyynl/ynl_gen_c.py", line 1147, in _load_nested_sets
child = self.pure_nested_structs.get(nested)
^^^^^^
UnboundLocalError: cannot access local variable 'nested' where it is not associated with a value
This appears to be a bug since there are existing specs which omit
"nested-attributes" on "multi-attr" attributes. Also, according to
Documentation/userspace-api/netlink/specs.rst, multi-attr "is the
recommended way of implementing arrays (no extra nesting)", suggesting
that nesting should even be avoided in favor of multi-attr.
Fix the indentation of the if-block introduced by the commit to avoid
the error.
Fixes: ce6cb8113c ("tools: ynl-gen: individually free previous values on double set")
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: https://patch.msgid.link/d6b58684b7e5bfb628f7313e6893d0097904e1d1.1746940107.git.lukas@wunner.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
aml_pctl_find_group_by_name() is not used anywhere, as reported by W=1
clang build:
pinctrl-amlogic-a4.c:600:2: error: unused function 'aml_pctl_find_group_by_name' [-Werror,-Wunused-function]
Fixes: 6e9be3abb7 ("pinctrl: Add driver support for Amlogic SoCs")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/20250509150114.299962-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix several build errors when CONFIG_MODULES=n, including the following:
../arch/x86/kernel/alternative.c:195:25: error: incomplete definition of type 'struct module'
195 | for (int i = 0; i < mod->its_num_pages; i++) {
Fixes: 872df34d7c ("x86/its: Use dynamic thunks for indirect branches")
Cc: stable@vger.kernel.org
Signed-off-by: Eric Biggers <ebiggers@google.com>
Acked-by: Dave Hansen <dave.hansen@intel.com>
Tested-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
The reserved-memory.yaml reference needs the full path. No warnings were
generated because the example has the wrong compatible string, so fix
that too.
Fixes: 304a90c4f7 ("dt-bindings: soc: fsl: Convert q(b)man-* to yaml format")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250507154231.1590634-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the TI OMAP2/3 interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
"ti,intc-size" property isn't actually used with "ti,omap2-intc", so the
2 bindings can be combined.
Link: https://lore.kernel.org/r/20250505144917.1294150-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the TI Wakeup Generator interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.
Link: https://lore.kernel.org/r/20250505144913.1293967-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the TI Keystone 2 interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144908.1293785-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the TS-4800 FPGA interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144856.1293370-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the SPEAr3xx Shared interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.
Link: https://lore.kernel.org/r/20250505144851.1293180-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Synopsys DW-APB interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.
Link: https://lore.kernel.org/r/20250505144842.1292840-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the ARC-HS incore interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144834.1292666-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the ARC-HS Interrupt Distribution Unit interrupt controller
binding to schema format. It's a straight-forward conversion of the
typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144830.1292495-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Qualcomm Atheros ath79 Misc interrupt controller binding to
schema format.
Adjust the compatible values to match what's actually in use.
Link: https://lore.kernel.org/r/20250505144821.1292151-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Marvell On-Die Message interrupt controller binding to
schema format.
Drop the 'interrupt-controller' property which isn't relevant for an MSI
controller.
Link: https://lore.kernel.org/r/20250505144727.1290271-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Marvell ICU interrupt controller to DT schema format.
Add the missing addressing properties to read and translate child node
addresses.
Drop the legacy binding description and example.
Link: https://lore.kernel.org/r/20250505144524.1285795-1-robh@kernel.org
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Marvell SEI interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144749.1290862-1-robh@kernel.org
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Marvell 7K/8K PIC interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.
Link: https://lore.kernel.org/r/20250505144715.1289866-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the TI-NSPIRE interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
'#interrupt-cells' was missing from the property list, but used in the
example, so add it.
Link: https://lore.kernel.org/r/20250505144711.1289677-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the J-Core advanced interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.
Link: https://lore.kernel.org/r/20250505144707.1289503-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the ImgTec Powerdown Controller (PDC) interrupt controller
binding to schema format. It's a straight-forward conversion of the
typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144703.1289335-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Google Goldfish PIC interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.
Link: https://lore.kernel.org/r/20250505144658.1289158-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the EZchip NPS interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.
Link: https://lore.kernel.org/r/20250505144649.1288786-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the C-SKY Multi-processor interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.
Link: https://lore.kernel.org/r/20250505144640.1288458-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the C-SKY APB interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144636.1288261-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Cirrus EP7209 interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144631.1288086-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Broadcom BCM6345 interrupt controller binding to schema
format.
The old schema indicated SoC specific compatibles should be present, but
there are none in use. So drop them.
The most number of CPUs on any platform seems to be 2, so document that
as the maximum.
Link: https://lore.kernel.org/r/20250505144622.1287712-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Amazon FIC interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144548.1286525-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Amazaon Alpine MSIX controller binding to schema format.
Drop the interrupt-controller property as the MSIX controller doesn't
provide interrupts. The interrupt-parent property is required in this
case for custom MSI mapping properties.
Link: https://lore.kernel.org/r/20250505144543.1286351-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
