Enable common modules for power management; one is to enable
CPUFREQ_DT driver; the driver is used by many platforms by passing OPP
table from device tree.
Also enables thermal related drivers. Firstly we need enable
configuration CPU_THERMAL for CPU cooling device driver, this will bind
thermal zone with CPU cooling device; and enable 'power allocator'
thermal governor.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- add PCIe driver for Aardvark for Armada 3700
- enable xhci-platform for A7K/A8K
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlfMQewACgkQCwYYjhRyO9WrKgCeJWuHOFUlMYoZqEYKkdA5aJ9G
iPsAoIFQivT7yCn9p7rJKzKt2NI4skoy
=jIwM
-----END PGP SIGNATURE-----
Merge tag 'mvebu-defconfig64-4.9-1' of git://git.infradead.org/linux-mvebu into next/arm64
Pull "mvebu defconfig64 for 4.9 (part 1)" from Gregory CLEMENT:
- add PCIe driver for Aardvark for Armada 3700
- enable xhci-platform for A7K/A8K
* tag 'mvebu-defconfig64-4.9-1' of git://git.infradead.org/linux-mvebu:
arm64: configs: enable PCIe driver for Aardvark
arm64: defconfig: enable xhci-platform
drivers/char/hw_random/Kconfig has 'default m', so
simply removing this entry from the defconfig will
enable building HW random drivers as modules.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable hisilicon SAS and XGE for hip05 and hip06
- Enable drm, powerkey, bluetooth and adv7511/adv7533 for hikey
- Add PINCTRL to HISI platform
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXyVBpAAoJEAvIV27ZiWZcqWcQALMdZkeDs5iIwihsrRMnVmj9
a/XA/xVFsZj8lys6LIhGWZ7L4BDZxLvF0065EeyVIDphhk51D5rgyYy2rP5SlDnj
kZJxB/RoycDrp95rOZGHaC1prN23mmk6gGT3BK6CW6OJKEZI+UNu+a0P2EfntGR2
vpGl4MeoI0GT2ZvpN0c2uzURHGof687mAgHbrNKDmKYKkHgV9hA2D2oFjWdYxcYB
fXh7a7d5vRpTrYIKo5R2T2XUDIUQuohgIWDdyDTUsFTPqEXt9Dict5R6k6dXTiCR
5SPKnZ8AgHU+wWTtB+A+XL5h+jbyftuymuaQY/iEESa/0e7xCWIRyk3wRYUKmNch
Q5w4tqVzqeZjALKE1Lshaw78+SMf/vKSp09LSIx60hRNpuEXm9H7iALxETsgl8Av
ofRD85K0HW18dhVTQoDB3hplqi485lSkkuigTX9R3TkE6iY2XitDJeseSxH/wHml
0alpDMXqv4WNvrLfunZdVqOoLEbuFoYhwhq5EHv94LZoyIacVsd5dx7bg6P3o7sj
3xRXyU3O7fSLc1Qr56+88i99PmbIX68B77V3xrwAJYW8kBGVdNci0ccLuVmlaSdc
B3FmLk+MCd2gofNzyYG8lQeXCRM+ElnhAZ+QC0vQhvUETdGXSpA+ZJcph/adaq/j
8im37ibx4oByG3TCk7w3
=y80h
-----END PGP SIGNATURE-----
Merge tag 'hisi-defconfig-for-4.9' of git://github.com/hisilicon/linux-hisi into next/arm64
Pull "ARM64: hisilicon: defconfig updates for 4.9" from Wei Xu:
- Enable hisilicon SAS and XGE for hip05 and hip06
- Enable drm, powerkey, bluetooth and adv7511/adv7533 for hikey
- Add PINCTRL to HISI platform
* tag 'hisi-defconfig-for-4.9' of git://github.com/hisilicon/linux-hisi:
Kconfig: ARCH_HISI: Add PINCTRL to HISI platform
arm64: defconfig: enable bluetooth supports as modules
arm64: defconfig: enable CONFIG_INPUT_HISI_POWERKEY for HiKey
arm64: defconfig: Enable HiSilicon kirin drm, adv7533 for HiKey
arm64: defconfig: Enable Hisi SAS and HNS
- Enable i.MX6 SATA and cpufreq driver support in multi_v7_defconfig.
- Enable MPL3115, Etnaviv GPU, WM8960 Codec driver and more USB
functions support in imx_v6_v7_defconfig.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJX1lztAAoJEFBXWFqHsHzOIdcIALyc4nkJXR1XYYTfL7h+KkgC
YozZ7dX2JyU4n+lYtRz1wLc9SANUu3Of6Ecipk+Y7Djnen0G5Qet6rP5NXzFwmVM
gy5OwctXUaWv7muynLf3SIFyFZ5b+mKwO2n2b/88E5mbSEUXskD/b8lYm/i4XHeJ
Ev3NfAaKo5eDCA39VNsNuD8XkC9wz5CaHbQNCR3hBmHUo9Fjh2eMcloy7/zcbXE9
tVIrZrIzge7l9s5UE1gMYvChQKPE/3tQRhS7NlqFAM4zQfbhQYN1UjibZfoizlMi
jWQxpjZo5VsVOZ1uHPPjdMbjOVHfnUWkSV/l6AAmo4Mnftt83Y3fFxQ+jPHIWgY=
=/Z7R
-----END PGP SIGNATURE-----
Merge tag 'imx-defconfig-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/defconfig
Merge "i.MX defconfig updates for 4.9" from Shawn Guo:
- Enable i.MX6 SATA and cpufreq driver support in multi_v7_defconfig.
- Enable MPL3115, Etnaviv GPU, WM8960 Codec driver and more USB
functions support in imx_v6_v7_defconfig.
* tag 'imx-defconfig-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx_v6_v7_defconfig: Select the wm8960 codec driver
ARM: imx_v6_v7_defconfig: Add CONFIG_MPL3115
ARM: imx_v6_v7_defconfig: Enable GPU support
ARM: imx_v6_v7_defconfig: enable more USB configurations
ARM: multi_v7_defconfig: Enable ARM_IMX6Q_CPUFREQ
ARM: multi_v7_defconfig: Enable AHCI_IMX
- update dsa config with new symbol
- add flash related config for mvebu v7
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlfMQVUACgkQCwYYjhRyO9XsjwCfXdMXmR+QEF+zFB/K/Z5E2BWO
RFYAnRWBOjELgMuH1Q14Sw8ANEj1H5/A
=ZV+v
-----END PGP SIGNATURE-----
Merge tag 'mvebu-defconfig-4.9-1' of git://git.infradead.org/linux-mvebu into next/defconfig
Pull "mvebu defconfig for 4.9 (part 1)" from Gregory CLEMENT:
- update dsa config with new symbol
- add flash related config for mvebu v7
* tag 'mvebu-defconfig-4.9-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu_v5_defconfig: use MV88E6XXX
ARM: mvebu: enable UBI and UBIFS in mvebu_v7_defconfig
ARM: mvebu: enable MTD command line partition table in mvebu_v7_defconfig
Keystone usb phy needs CONFIG_NOP_USB_XCEIV to be enabled.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXx15hAAoJEHJsHOdBp5c/4i4P/iOGMsKUNltw1qiqN5nihF0V
GWaaVk/vz1oXjm98CyfPOPK9+u5SioRrm04nzhQdSTUmqZNtGJg1PKWjtJcyKuQZ
ajZpD+1QdviFJw+/Gffdxsw38W5nQ6X5//IzSYR68CWXet11zrujBJA4GK7Mxs3Y
fFkehrBIgcgeIdwIRx8HuZWu1+xtVDWwXIc5f/LxoIATffaSMTMapW8QTiPvvWxk
HB+p8LshwPAS71vnzC4GUHPinEVLawesPLUDxq56e+DCKspq20UsOWezc/JEvUNL
X2IXvODFx+9WyIdgErdt0+00ljiVw4KWEGexAaYqVUmmbSARA45/vULUkoOZ6qIY
u8vy3L58A2E7KvLi2U5ma5mHzRs7bSOuoFO9hhjSLG1nbjyz3HcPmYgTXyP9hCPR
L16nwlrcAsc4M+u7HD7RR7vuUteQcqhYo8cLsDJjwJcwyicmIGRewBQI3to1s5sJ
h8iu1atoJC4yPvTEpI8iflpuqkCMfvntkvOlmiyVJ0EyEPxBNli8QKOo2tq1MfSZ
J4rHWQq8DB8EWoqkrEC8hnRof2Sa//0B44AXffujwzdng+LiYVBYbbSmQ8Q/L86T
l7WN2a+mqfYfJPrxB7lF9WzH14fy7SVCOuuxmJqdAYImw4/QBm6ecBkkH6JhGXdL
+OAXb4QFg7YC7+c7BtBn
=jzCV
-----END PGP SIGNATURE-----
Merge tag 'keystone_config_for_4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/defconfig
Pull "ARM: config: Add CONFIG_NOP_USB_XCEIV" from Santosh Shilimkar:
Keystone usb phy needs CONFIG_NOP_USB_XCEIV to be enabled.
* tag 'keystone_config_for_4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
ARM: keystone: defconfig: Fix USB configuration
artpec6_add_pcie_port() is called from artpec6_pcie_probe(), which is not
marked __init. It is wrong to call an __init function from a non-__init
one, so remove __init from artpec6_add_pcie_port().
[bhelgaas: changelog]
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The R-Car PCIe driver causes 13 warnings from scripts/checkpatch.pl --
let's fix at least 10 easier ones:
- line over 80 characters;
- blank line missing after declarations;
- statements not starting on a tabstop.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Implement the MSI .setup_irqs() method which enables allocation of several
MSIs at once.
[Sergei Shtylyov: removed unrelated/unneeded changes, fixed too long lines,
reordered the variable declarations, reworded the summary/description.]
Signed-off-by: Grigory Kletsko <grigory.kletsko@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
This reverts the Tegra part of commit 797da5598f (PM / devfreq: Add
COMPILE_TEST for build coverage) that introduced a build failute in
in linux-next.
[ rjw: Changelog ]
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Enumeration
Mark Haswell Power Control Unit as having non-compliant BARs (Bjorn Helgaas)
Power management
Fix bridge_d3 update on device removal (Lukas Wunner)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJX2az0AAoJEFmIoMA60/r8/EoP/28mGRiKi8mlqNAR3MYN3F0n
VSIm7WyxWNawH1gRJXKQBzNqgMJnj4qRGXSIvP3AIYyBDcJs/X7j91/eKOARNfQr
55A+gfSz4jUKlw+0WgPY8/U2/xQ4yoom1zhbsAYcIVeljZo/3JUg+wHpPjhIMkH0
2slTerHRDExrS43jxQi225toiEaO6lcY8EVmHCDo+jYlQz3sCEwIXg9hn1rwTbvG
sJI0zyUwHF+oWowgJqlwYxsbPPnelPAN5YAx7KrHuVmBdL0Bgo3oIRtbb3JZZ9Up
L9bQ6NpRjSARvijaZ2TAhueqIIDv2HGgvwNB01l4Yggw7Sm1dFCuUS6vj/e5tpZA
xntE3F6s2Z+I4I1D7pAX3jMYCdYx/QltiTCeGRp8pJv+f4ewW3jcel3FAksY3BEg
0NCjDrGFqGYai4hGRROpt/aXlW/Pn53eQLlu4Xg2qgkj0NMh0ODMrTjMnABB39ae
eGqIXab7WeVBxt10eU19J1u1RTqpUO2LJW+cMnvYdCfKAYby/gj8SD8vIsn3oDjZ
hQS/4fSHurc7LZwDmwOfaiHlGnvcQWV9EKwgScS0v8AxPQnC8pNUgYpzZcXY8Q6I
YXtyK7suFriSZPS0Qs4FrdfJrmTBaBQ55aZu9aftb5v4YqacN5qZo+HaXiONBy3v
RzsFK6xIbnIgb35g8vKy
=PQml
-----END PGP SIGNATURE-----
Merge tag 'pci-v4.8-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI fixes from Bjorn Helgaas:
"Here are two changes for v4.8. The first fixes a "[Firmware Bug]: reg
0x10: invalid BAR (can't size)" warning on Haswell, and the second
fixes a problem in some new runtime suspend functionality we merged
for v4.8. Summary:
Enumeration:
Mark Haswell Power Control Unit as having non-compliant BARs (Bjorn Helgaas)
Power management:
Fix bridge_d3 update on device removal (Lukas Wunner)"
* tag 'pci-v4.8-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: Fix bridge_d3 update on device removal
PCI: Mark Haswell Power Control Unit as having non-compliant BARs
Add X-Gene PMD clock support.
PMD clock is implemented for a single register field.
Output rate = parent_rate * (denominator - scale) / denominator
with
- denominator = bitmask of register field + 1
- scale = values of register field
For example, for bitmask is 0x7, denominator will be 8 and scale
will be computed and programmed accordingly.
Signed-off-by: Hoan Tran <hotran@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The ZX296718 clocks are statically listed and registered. More
clock will be added later.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add power down bit and pll lock bit in pll config structure
to ease new SoC support.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The ZX296718 clocks are statically listed and registered. More
clock will be added later.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add power down bit and pll lock bit in pll config structure
to ease new SoC support.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* dt/irq-fix:
arm64: dts: Fix broken architected timer interrupt trigger
This resolves a non-obvious conflict between a bugfix from
v4.8 and a cleanup for the exynos7 platform.
A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Reviewed-by: Alex Elder <elder@linaro.org>
[sboyd@codeaurora.org: Save a line]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.
The respective maintainers are of course welcome to prove me wrong.
While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Per the PCI Firmware spec, r3.0, sec 4.5.1, on ACPI systems, the OS must
not use AER unless _OSC is present and _OSC grants AER control to the OS.
The aerdriver.forceload kernel parameter was a way to enable Linux AER
support on ACPI systems that lack _OSC or fail to grant control the the OS.
Enabling Linux AER support when the firmware doesn't want us to is a recipe
for problems, e.g., the firmware might be handling AER itself.
Remove the aerdriver.forceload kernel parameter and related supporting
code.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The aerdriver.nosourceid kernel parameter was intended for working around
broken chipsets don't supply the source ID for AER events. We recently
added PCI_BUS_FLAGS_NO_AERSID, which can be set by quirks for the same
purpose.
Remove the aerdriver.nosourceid kernel parameter. For anything other than
debugging, asking users to find and use kernel parameters is a poor user
experience. Instead, we should add PCI_BUS_FLAGS_NO_AERSID quirks for any
hardware that needs it.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The current irq spreading infrastructure is just looking at a cpumask and
tries to spread the interrupts over the mask. Thats suboptimal as it does
not take numa nodes into account.
Change the logic so the interrupts are spread across numa nodes and inside
the nodes. If there are more cpus than vectors per node, then we set the
affinity to several cpus. If HT siblings are available we take that into
account and try to set all siblings to a single vector.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Christoph Hellwig <hch@lst.de>
Cc: axboe@fb.com
Cc: keith.busch@intel.com
Cc: agordeev@redhat.com
Cc: linux-block@vger.kernel.org
Link: http://lkml.kernel.org/r/1473862739-15032-3-git-send-email-hch@lst.de
For irq spreading want to store affinity masks in the msi_entry. Add the
infrastructure for it.
We allocate an array of cpumasks with an array size of the number of used
vectors in the entry, so we can hand in the information per linux interrupt
later.
As we hand in the number of used vectors, we assign them right
away. Convert all the call sites.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: axboe@fb.com
Cc: keith.busch@intel.com
Cc: agordeev@redhat.com
Cc: linux-block@vger.kernel.org
Cc: Christoph Hellwig <hch@lst.de>
Link: http://lkml.kernel.org/r/1473862739-15032-2-git-send-email-hch@lst.de
Due to the use of READ_ONCE() in list_empty() the compiler cannot
optimise !list_empty() ? list_first_entry() : NULL very well. By
manually expanding list_first_entry_or_null() we can take advantage of
the READ_ONCE() to avoid the list element changing under the test while
the compiler can generate smaller code.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Jan Kara <jack@suse.cz>
Cc: Josef Bacik <jbacik@fb.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Introduce new flags that defines which ABI to use on creating sigframe.
Those flags kernel will set according to sigaction syscall ABI,
which set handler for the signal being delivered.
So that will drop the dependency on TIF_IA32/TIF_X32 flags on signal deliver.
Those flags will be used only under CONFIG_COMPAT.
Similar way ARM uses sa_flags to differ in which mode deliver signal
for 26-bit applications (look at SA_THIRYTWO).
Signed-off-by: Dmitry Safonov <dsafonov@virtuozzo.com>
Reviewed-by: Andy Lutomirski <luto@kernel.org>
Cc: 0x7f454c46@gmail.com
Cc: oleg@redhat.com
Cc: linux-mm@kvack.org
Cc: gorcunov@openvz.org
Cc: xemul@virtuozzo.com
Link: http://lkml.kernel.org/r/20160905133308.28234-7-dsafonov@virtuozzo.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
As the task isn't executing at the moment of {GET,SET}REGS,
return regset that corresponds to code selector, rather than
value of TIF_IA32 flag.
I.e. if we ptrace i386 elf binary that has just changed it's
code selector to __USER_CS, than GET_REGS will return
full x86_64 register set.
Note, that this will work only if application has changed it's CS.
If the application does 32-bit syscall with __USER_CS, ptrace
will still return 64-bit register set. Which might be still confusing
for tools that expect TS_COMPACT to be exposed [1, 2].
So this this change should make PTRACE_GETREGSET more reliable and
this will be another step to drop TIF_{IA32,X32} flags.
[1]: https://sourceforge.net/p/strace/mailman/message/30471411/
[2]: https://lkml.org/lkml/2012/1/18/320
Signed-off-by: Dmitry Safonov <dsafonov@virtuozzo.com>
Cc: 0x7f454c46@gmail.com
Cc: oleg@redhat.com
Cc: linux-mm@kvack.org
Cc: luto@kernel.org
Cc: Pedro Alves <palves@redhat.com>
Cc: gorcunov@openvz.org
Cc: xemul@virtuozzo.com
Link: http://lkml.kernel.org/r/20160905133308.28234-6-dsafonov@virtuozzo.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Long ago, we updated a "switch_save" field based on the latch status. But
switch_save was unused, and ed6cbcf2ac ("[PATCH] pciehp: miscellaneous
cleanups") removed it.
We no longer use the latch status, so remove calls to
pciehp_get_latch_status(). No functional change intended.
Tested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Print slot name consistently as "Slot(%s)". I don't know whether that's
ideal, but we can at least do it the same way all the time. No functional
change intended.
Tested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
In pcie_isr(), we return early if no status bits other than
PCI_EXP_SLTSTA_CC are set. This was introduced by dbd79aed1a ("pciehp:
fix NULL dereference in interrupt handler"), but it is no longer necessary
because all the subsequent pcie_isr() code is already predicated on a
status bit being set.
Remove the unnecessary test for ~PCI_EXP_SLTSTA_CC. No functional change
intended.
Tested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Previously we read Slot Status when handling a surprise event. But Slot
Status might have changed since we identified the event, and the event_type
already tells us whether to enable or disable the slot, so there's no need
to read it again.
Remove handle_surprise_event() and queue the power work directly.
[bhelgaas: changelog]
Tested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Mayurkumar Patel <mayurkumar.patel@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Rajat Jain <rajatxjain@gmail.com>
Previously we read Slot Status to learn about hotplug events, then cleared
the events, then re-read Slot Status to find out what happened. But Slot
Status might have changed before the second read.
Capture the Slot Status once before clearing the events. Also capture the
Link Status if we had a link status change.
[bhelgaas: changelog, split to separate patch]
Tested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Mayurkumar Patel <mayurkumar.patel@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Previously we accumulated hotplug events, then processed them, essentially
like this:
events = 0
do {
status = read(Slot Status)
status &= EVENT_MASK # only look at events
events |= status # accumulate events
write(Slot Status, events) # clear events
} while (status)
process events
The problem is that as soon as we clear events in Slot Status, the hardware
may send notifications for new events, and we lose information about the
first events. For example, we might see two Presence Detect Changed
events, but lose the fact that the slot was temporarily empty:
read PCI_EXP_SLTSTA_PDC set, PCI_EXP_SLTSTA_PDS clear # slot empty
write PCI_EXP_SLTSTA_PDC # clear PDC event
read PCI_EXP_SLTSTA_PDC set, PCI_EXP_SLTSTA_PDS set # slot occupied
The current code does not process a removal; it only processes the
insertion, which fails because we didn't remove the original device.
To avoid this problem, read Slot Status once and process all the events
before reading it again, like this:
do {
read events
clear events
process events
} while (events)
[bhelgaas: changelog, add external loop around pciehp_isr()]
Tested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Mayurkumar Patel <mayurkumar.patel@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
