cci_pmu_sync_counters and pmu_event_set_period are internal functions
to the CCI PMU driver, so make them static to avoid polluting the kernel
namespace.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add ARM CoreLink CCI-550 cache coherent interconnect PMU
driver support. The CCI-550 PMU shares all the attributes of CCI-500
PMU, except for an additional master interface (MI-6 - 0xe).
CCI-550 requires the same work around as for CCI-500 to
write to the PMU counter.
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
CCI-550 PMU shares most of the CCI-500 PMU attributes including the
event format, PMU event codes. The only difference is an additional
master interface (MI6 - 0xe). Hence we share the driver code for both,
except for a model specific event validate method.
This patch renames the common CCI500 symbols to CCI5xx, including the
Kconfig symbol.
No functional changes to the PMU driver.
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The CCI PMU driver sets the event counter to the half of the maximum
value(2^31) it can count before we start the counters via
pmu_event_set_period(). This is done to give us the best chance to
handle the overflow interrupt, taking care of extreme interrupt latencies.
However, CCI-500 comes with advanced power saving schemes, which
disables the clock to the event counters unless the counters are enabled to
count (PMCR.CEN). This prevents the driver from writing the period to the
counters before starting them. Also, there is no way we can reset the
individual event counter to 0 (PMCR.RST resets all the counters, losing
their current readings). However the value of the counter is preserved and
could be read back, when the counters are not enabled.
So we cannot reliably use the counters and compute the number of events
generated during the sampling period since we don't have the value of the
counter at start.
This patch works around this issue by changing writes to the counter
with the following steps.
1) Disable all the counters (remembering any counters which were enabled)
2) Enable the PMU, now that all the counters are disabled.
For each counter to be programmed, repeat steps 3-7
3) Save the current event and program the target counter to count an
invalid event, which by spec is guaranteed to not-generate any events.
4) Enable the target counter.
5) Write to the target counter.
6) Disable the target counter
7) Restore the event back on the target counter.
8) Disable the PMU
9) Restore the status of the all the counters
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add a hook for writing to CCI PMU counters. This callback
can be used for CCI models which requires some extra work
to program the PMU counter values. To accommodate group writes
and single counter writes, the call back accepts a bitmask
of the counter indices which need to be programmed with the
given value.
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
On CCI-500 writing to a counter requires turning the PMU on. So,
synchronising the counter state should not be performed for such special cases,
while turning the PMU on. This patch adds a helper, __cci_pmu_enable_nosync(),
without flushing the counter states.
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Adds helper routines to disable the counter controls for
all the counters on the CCI PMU and restore it back, by
preserving the original state in caller provided mask.
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add helper routines to check if the counter is enabled or not.
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
pmu_write_counter() is now only called from pmu_write_counters(),
which does so for each set index in the given mask, bounded by
cci_pmu->num_cntrs. So, there is no need for an extra check to
make sure the given counter is valid inside pmu_write_counter.
This patch gets rid of that.
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
CCI PMU driver always reprograms the counters to a safe value (half of the
counter max, = 2^31) before starting the profiling to account for extreme
interrupt latencies. Also, the cost of writing to a PMU counter could be
very costly on some PMUs(e.g, CCI-500). In order to ammortise the cost of
programming the counters, this patch delays the counter writes to pmu::pmu_enable().
We use the PER_HES_ARCH flag to keep track of the counters which need to
be programmed. Before turning on the PMU, we go through the counters that
were marked for write, and perform the operation in a batch.
To unify all the counter writes to pmu_enable(), this patch also makes sure that
we disable-and-enable the PMU in the irq handler to program any counters that
overflowed.
Cc: Punit Agrawal <punit.agrawal@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This patch refactors the CCI PMU driver code a little bit to
make it easier share the code for enabling/disabling the CCI
PMU. This will be used by the hooks to work around the special cases
where writing to a counter is not always that easy(e.g, CCI-500)
No functional changes.
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add a helper to group the writes to PMU counter, this will be
used to delay setting the event period to pmu::pmu_enable()
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
cpumask_any_but returns value >= nr_cpu_ids if there are no more CPUs.
The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
There's no need to dynamically initialise attribute pointers when we can
get the compiler to do it for us. We also don't need a dev_ext_attribute
for the cpumask, as the drvdata for a PMU device is a pointer to struct
pmu.
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
clock to control ehrpwm tbclk.
The TRM says, tbclk is derived from SYSCLKOUT. SYSCLKOUT is nothing but
ehrpwm functional clock derived from the gateable interface and
functional clock of PWMSS(l4_root_clk_div).
Refer AM57x TRM SPRUHZ6[1], October 2014, Table 29-4 and Section 29.2.2.1,
Table 29-19 and the NOTE at the end of the table.
[1] www.ti.com/lit/ug/spruhz6/spruhz6.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit cbce790059 ("PCI: designware: Make driver arch-agnostic") changed
the host bridge sysdata pointer from the ARM pci_sys_data to the DesignWare
pcie_port structure, and changed pcie-designware.c to reflect that. But it
did not change the corresponding code in pci-keystone-dw.c, so it caused
crashes on Keystone:
Unable to handle kernel NULL pointer dereference at virtual address 00000030
pgd = c0003000
[00000030] *pgd=80000800004003, *pmd=00000000
Internal error: Oops: 206 [#1] PREEMPT SMP ARM
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.2-00139-gb74f926 #2
Hardware name: Keystone
PC is at ks_dw_pcie_msi_irq_unmask+0x24/0x58
Change pci-keystone-dw.c to expect sysdata to be the struct pcie_port
pointer.
[bhelgaas: changelog]
Fixes: cbce790059 ("PCI: designware: Make driver arch-agnostic")
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v4.4+
CC: Zhou Wang <wangzhou1@hisilicon.com>
- a single fix for nand dmaengine node
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0aHhAAoJEAP2et0duMsS3scP/R9XbJvMbMEXNw3gODLHFGHa
65GBlWTx4cB0zkOdOt3nO/NAKqwTyB9q1+7Pz7D0ujy9ASlomVU+GNbX/J78pBDD
2uOS6PcHfgUMQ6/FjfwIe8FS3jIAcZMXcVyyuzV4x2uWPCBlL5tisQles8kcPo+d
WRYiizsBuh0wH+qfav0jdUUiKSHhI/MPhxoRg16YqNK01zcTz7GA18HerjnNLk91
Ak2NDFBy9PN8fukrGcTqSE6Aree0wdWPOYi4PPDvNmujoEKz8S2ayoVw2yYp6Sn1
OmyMy8JOoB2I3BCG2LdKw6b3ZnBhBEPUOFbHf7c/E8bQXJlhZXwB2pYAAydnUmgm
GBKt6y/gn50NqR5X2ikn9+NNlzW9QLxd5x2gsky1QYy/akeNqR8eg1+OULv2p2pW
HgsolSTpOOGM7YtH6ihngs8xYUira6kQ41MRfhkE6Tx4t+vua4MQUV3gn+bMXzRN
9j46zgmqkKO33NCbKSXcH5pz36J/kONFT5zExH2q2MJocuN9KZw30mmngkxJiwtq
lddZxDYGQ6fTDvi3dL0YoR8X3tns4xUrM9FsONFUBH5r7dhROpMtKfQTxzYaFLgW
S0kpXjItvGCqhQOT1an/lKW0I6+Y0oJglQnobsrxJHte2RRGwwUtI/A1vgvUGB9o
9dPX01NV+7wFsOVyuKbi
=4uk1
-----END PGP SIGNATURE-----
Merge tag 'pxa-dt-4.6' of https://github.com/rjarzmik/linux into next/dt
Merge pxa dt for v4.6 from Robert Jarzmik:
This device-tree pxa update brings :
- a single fix for nand dmaengine node
* tag 'pxa-dt-4.6' of https://github.com/rjarzmik/linux:
ARM: dts: pxa: fix dma engine node to pxa3xx-nand
Quite a few changes, among which:
- Support for the A83t
- Support for the eMMC DDR on a few boards
- Support for the OTG controller on a few boards
- New boards: Itead Ibox, Cubietruck plus, Homlet v2, Lamobo R1
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0KoYAAoJEBx+YmzsjxAgV9UP/1VVx1sWS1CgZ3tPdHMlznM+
l5ehkZXHg3rATh3bM+j9HXv5j158Jiq5Hhx+XQ2/xM+dM3iuNRsszhG9RwN9uWMg
LnYbxSQ65kdf2rSysQNn+7FQjZU4d5Lt6nkAuLyLH/1g6Vqz8CERhEhFOV63q+i2
s5W7yaLe5QyqlCBQ9wXCC9ZbPBzUPAggrHSuQlSkIK5GAVBcgzCuZFEwj+NCgCSt
VXOF9tPU64CREsKcMKhC8TIltc91d2A9xEVQuLxHDk7ywD81fOnjNfmiFbklQHr+
AfzKR0REJLP3T8hKBkbAxNbiKhiHDJ6xDSb/a7DbVELMf03U4VtUH17CnCE4ZNdb
fEIcddLoTJc76tlePlBFVNblC8+/Feefw5SrkwYjhd/gP46uy8MP+3RS+8MluXih
uNucj+Ge03qztYR4RatG154qeAkuolzLNXxDOtp45d6KhqG8E1lVVOSXr+d1dSiU
GF0sl84ZtlWqIKs7Vo1Oss1W7vdUAOLrzUOQt8077uGHo/EatPRwoUQ7nKAy2rne
evCDJl0f3VknxG+BSdky0I7NVvmJy/mWHRLXdxV9AOx1RPfNWxgUZNVKhJLLqNhv
2fut4C31t/CHwrD8XsxaCAHfcwXLIOaJBak/9QGh9pJK4+RkQ2JaTvbgnAEsCth/
+vt04W2rK4secDExX21A
=CJtp
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt
Merge "Allwinner DT Additions for 4.6" from Maxime Ripard:
Quite a few changes, among which:
- Support for the A83t
- Support for the eMMC DDR on a few boards
- Support for the OTG controller on a few boards
- New boards: Itead Ibox, Cubietruck plus, Homlet v2, Lamobo R1
* tag 'sunxi-dt-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (34 commits)
ARM: dts: sun8i: Add leds and switch on Orangepi Plus boards
ARM: dts: sun8i: Add ir receiver nodes to H3 dtsi
ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
dts: sun8i-h3: Add APB0 related clocks and resets
ARM: dts: sun7i: Add dts file for the lamobo-r1 board
ARM: dts: sun4i: Enable USB DRC on Hyundai-a7hd
ARM: dts: sun4i: Enable USB DRC on the MK802
ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes
ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes
ARM: dts: sun7i: Enable USB DRC on Olimex A20 EVB
ARM: dts: sun7i: Enable USB DRC on MK808C
ARM: dts: sunxi: Fix #interrupt-cells for PIO in H3
ARM: dts: sun8i-a83t: Correct low speed oscillator clocks
ARM: dts: sun9i: a80-optimus: Remove i2c3 and uart4
ARM: dts: sun4i: Itead Iteaduino to use common code
ARM: dts: sun7i: Add Itead Ibox support
ARM: dts: sunxi: Add sunxi-itead-core-common.dtsi
ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC
ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC
ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins
...
A bunch of changes to add new drivers to the sunxi and multi_v7 defconfigs,
most notably the USB OTG that is finally enabled.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0J8dAAoJEBx+YmzsjxAgqlMP/1a2IaPeM5bYb/Enu2Creqod
+mc03J1xYBVTLqXnELX6j7ydxVa0ZknQlbMQV7FiQ6icdaS+KwK6vx7kGTogEXtr
ZxwNsTlW/n948ewr6snZlkXzdPORp2t6UKfgjJwo2UtITcPTBTUxItUZpssqNZ8B
T79S0v1YJkdHb5ulcii8SzgwyE8Gs55KnCddbCE3h59sqb0mNEOz7sdOg94JlR9Q
nM+JtoKPSiG9yHUaC+/Rpad02Ahr0735acD58nSUIteNHMdqAqFB7UKGkYp5NoT0
B1A9+5nSysDi/kynP7luHhBwNGieXfN+1z6Kfl1nl2kvJAOSDZM32b0pLMZ9FaXq
Oo2kykr5OLwNiZdPWpuU80a8lfH9zyVK61wJdnxn7Fdwy7fToHMgXdEZxDXnTI6K
FZHab6diaKb+Ob+ke14ZVqNZL6bLc0Ffjbha5jWpxOsroFNHMjzmY8Wn2x74BEDv
X7e8jxkyzUPy3MrIQ5NuT7fIhmj6NurBpcJ9+6URBUbkXpJ7zK50H1eyLiJh+6yk
uRIVYq0unLF27zcn/zrnePSLQkq6/pfdT3DS7qNZaAXnx0y8+Ij7UjvM+65BIe9s
uW+NnkGBchRbWFGXxvkLldFrUEsQrouSqdpEgGmOVub2evlnwnEVqeyJ3ar1QC4B
Odw0PD0tB9xYI/YQ/flR
=6Cse
-----END PGP SIGNATURE-----
Merge tag 'sunxi-defconfig-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/defconfig
Merge "Allwinner defconfig changes for 4.6" from Maxime Ripard:
A bunch of changes to add new drivers to the sunxi and multi_v7 defconfigs,
most notably the USB OTG that is finally enabled.
* tag 'sunxi-defconfig-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi_defconfig: Enable MUSB HDRC driver with Allwinner glue
ARM: multi_v7_defconfig: Enable A10 audio codec driver as module
ARM: multi_v7_defconfig: Enable MUSB HDRC driver with Allwinner glue
ARM: sunxi_defconfig: Enable INPUT_EVDEV so axp20x-pek can be used
ARM: sunxi_defconfig: Enable A10 audio codec driver
ARM: sunxi_defconfig: Enable sunxi IR driver
Just introduce the A83T support.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0J4RAAoJEBx+YmzsjxAglusP/AzXzEt4riBOkm9lj+bfBWGq
oP+Mnws/ySwqeLuEIeWRyICBm4BUvOgJKNBhE8ZOw3BnRFyUPyklw6B8NFSoWdZq
rBXtZ8sozfo3ru265PiftJxq7ZDTEk4N5Q3VhBqsv3iC0vCqdXNZipPW0bb/1LUW
thTvwuQnihnflLzsCRrRUcUEpyhbtX6vyu4DIGYdDtzRHyU/eo0rN2B+Mjs/9zA2
KqpWslopnk+hwaLSr5kF+7hSnmraQPhXHM+KlaMHkr6zxLpk4VA7bhNZ/DpzVRY9
w9uIoKDwFp8ErEiVyL3ID8Ce/NfWRVnjxKNKKDinxuzzc5gTHiji8dfjxi19BMYP
yeXfLwHw/stqwTpA7bii20F8VN/GwM7/wxNXdf0aDZRi2guM8S28Zqh0DiqnYwRU
lpszXBe3+4xjZs32fze/R2CPAlaF5LGYYj7z4n/EVHhuvV70IrTmNj8xcOi6Zhx3
BBSCp9SV9YX+f+xKpLJjcrSqE/RX5mJxfrwSGb4Kp75ISQQL4r1gijbExP+/O/sy
1ow3jfImCEB1owD9cjwPoEy0Ajt7GSkO1iryp0C0VZkeSNUqLHZIO/qYpZfVqRN0
Ukprvi45ly0ieojmcrbbWjq/kMiVoH6mye5tQ34Gfd3RJsSS1FNTF6AO2k8dg4xm
28VetJwcSY1lrttURUw0
=7u3U
-----END PGP SIGNATURE-----
Merge tag 'sunxi-core-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc
Merge "Allwinner core changes for 4.6" from Maxime Ripard:
Just introduce the A83T support.
* tag 'sunxi-core-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi: Introduce Allwinner for A83T support
Not a lot of changes for this kernel release, just a new Kconfig option and
some changes to the arm64 defconfig to add Allwinner drivers
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW0J0XAAoJEBx+YmzsjxAgA1MP/0wYih4KBFguL+me5G7EaI1T
AWwZQ2ONhUzLv3hXExOgJkorgIWtx6GdMvhvmsfbcIvuhuT+E8b5zclQnAECGXCl
XC91kIsHIEk4U3q4a4UJuUkr+/30j/GKsV2cQwM8ag1RThx7Kk6/dznNQmpElp3f
l/2LSUrFHctWnOWrauSFKzTVzb8Y1jZu/L/0odffkfLyzhBDL7ZvXNmQUCTKacxv
lmOqGVeL79TPdR3AGkv/SPqSMAN2vjp9HLGHg75zi9ThxaouDGJ3+DGUg22Ss/G7
NfOs+KFGJ8hjUU4AG5pm6o50AKBEaJ8y1EVe+B5YvVc9bburuot6MhvskYXIH32q
bMyzf7IkulxnEMaePKFBasOqNW7PfvbV5jddh8CYIImAz6qwHY77uv1+OGJcyHFu
xLbsta7/KZctW4NjsYb+Bew5aTj0Ntx/azZrm7QI+bJ1cutUODmefgO6NuNGKGgt
oLi9ZS4u990J1HbPJhy3Er8mXrC01G06/H8FewA6RA37VRzLZnnKxOfOoJB7fhbK
OmWRXVGz455KxP8u30TOK00ryxSBtCDmA85WojLoOvyhp9nHu5msP/KeCkrvLxev
qkSTmEAzh3nOC2FtbxoqTjuRodTSvvO5RVYffUr4MtBX/4VGWoPbMDY0kUmEBQIb
maqSKkZDccTkINrKAVPZ
=xgyy
-----END PGP SIGNATURE-----
Merge tag 'sunxi-config64-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/arm64
Merge "Allwinner configuration changes for ARM64, 4.6 edition" from Maxime Ripard:
Not a lot of changes for this kernel release, just a new Kconfig option and
some changes to the arm64 defconfig to add Allwinner drivers
* tag 'sunxi-config64-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
arm64: add defconfig options for Allwinner SoCs
arm64: Introduce Allwinner SoC config option
DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
represent this in memory dt node, the address-cells and size cells
should be 2. So, changing the address-cells and size-cells to 2 and
updating the memory nodes accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add initial support for Armada 7K/8K
Update Marvell documentation
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQXX4ACgkQCwYYjhRyO9V/HwCdF0ehY/nvq3czV19MjuG6ZZGL
IUIAn3bzCXq/AB42cd8heU9NDUSzNVpi
=1eah
-----END PGP SIGNATURE-----
Merge tag 'mvebu-arm64-4.6-2' of git://git.infradead.org/linux-mvebu into next/arm64
Merge "mvebu arm64 for 4.6 (part 2)" from Gregory CLEMENT:
Add initial support for Armada 7K/8K
Update Marvell documentation
* tag 'mvebu-arm64-4.6-2' of git://git.infradead.org/linux-mvebu:
arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
Documentation: arm: add Marvell Armada 7K and 8K families
Documentation: arm: add link to Armada 38x Functional Spec
Documentation: arm: improve Armada 37xx description
Documentation: arm: update Marvell product listing
enable SRAM support in mvebu_v7_defconfig
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQXRoACgkQCwYYjhRyO9XuDwCggDihNDvg28PdaATDslAWggt0
uJoAoIZioUyUwXZ2a0artKxtvxgBXme0
=+WFN
-----END PGP SIGNATURE-----
Merge tag 'mvebu-defconfig-4.6-2' of git://git.infradead.org/linux-mvebu into next/defconfig
Merge "mvebu defconfig for 4.6 (part 2)" from Gregory CLEMENT:
enable SRAM support in mvebu_v7_defconfig
* tag 'mvebu-defconfig-4.6-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: enable SRAM support in mvebu_v7_defconfig
The LP872x regulator is used in the LG Optimus Black codename sniper to supply
the external mmc card.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- Reorder Ethernet node on Armada 38x SoCs
- Add device tree for buffalo linkstation ls-gl
- Use the more accurate armada-370-sata string for SATA on Armada 375
- Add NAND description to Armada 370 DB and Armada XP DB
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQXKwACgkQCwYYjhRyO9VVYwCgpjGDDOuqbNWtj5NI3TS9gHsI
FLkAn1kS66eVLwf+0ptrOtu8nsu9mLql
=O+/a
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.6-2' of git://git.infradead.org/linux-mvebu into next/dt
Merge "mvebu dt for 4.6 (part 2)" from Gregory CLEMENT:
- Reorder Ethernet node on Armada 38x SoCs
- Add device tree for buffalo linkstation ls-gl
- Use the more accurate armada-370-sata string for SATA on Armada 375
- Add NAND description to Armada 370 DB and Armada XP DB
* tag 'mvebu-dt-4.6-2' of git://git.infradead.org/linux-mvebu:
ARM: dts: mvebu: add NAND description to Armada 370 DB and Armada XP DB
ARM: dts: armada-375: use armada-370-sata for SATA
ARM: dts: orion5x: add device tree for buffalo linkstation ls-gl
ARM: dts: orion5x: split linkstation lswtgl into common and device parts
ARM: dts: armada-38x: add reference to ETH connectors for A385-AP
ARM: dts: armada-38x: change order of ethernet DT nodes on Armada 38x
ARM: dts: orion5x: fix the missing mtd flash on linkstation lswtgl
ARM: dts: kirkwood: use unique machine name for ds112
In the PCI hotplug path of the Intel IOMMU driver, replace
the usage of the BUS_NOTIFY_DEL_DEVICE notifier, which is
executed before the driver is unbound from the device, with
BUS_NOTIFY_REMOVED_DEVICE, which runs after that.
This fixes a kernel BUG being triggered in the VT-d code
when the device driver tries to unmap DMA buffers and the
VT-d driver already destroyed all mappings.
Reported-by: Stefani Seibold <stefani@seibold.net>
Cc: stable@vger.kernel.org # v4.3+
Signed-off-by: Joerg Roedel <jroedel@suse.de>
randconfig warning fixes for mvebu SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQWXIACgkQCwYYjhRyO9WZUACgp08rrriNCYNTuR0KWkcus/T2
nX8AnRkwtcKvFO3dYGw6plWxMUFIyk5E
=n4KR
-----END PGP SIGNATURE-----
Merge tag 'mvebu-soc-4.6-1' of git://git.infradead.org/linux-mvebu into next/fixes-non-critical
Merge "mvebu soc for 4.6 (part 1)" from Gregory CLEMENT:
randconfig warning fixes for mvebu SoCs
* tag 'mvebu-soc-4.6-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: mark mvebu_hwcc_pci_nb as __maybe_unused
ARM: mv78xx0: avoid unused function warning
ARM: orion: only select I2C_BOARDINFO when using I2C
Add a missing call to of_node_put() armada_xp_smp_prepare_cpus()
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQWGcACgkQCwYYjhRyO9XC3QCfQRlD4Is9IhQPmFnQ7d48TixY
k2IAn3OX5cNsG0dUzUJ8EOOTDEOLqBvV
=8cY9
-----END PGP SIGNATURE-----
Merge tag 'mvebu-cleanup-4.6-2' of git://git.infradead.org/linux-mvebu into next/cleanup
Merge "mvebu cleanup for 4.6 (part 2)" from Gregory CLEMENT:
Add a missing call to of_node_put() armada_xp_smp_prepare_cpus()
* tag 'mvebu-cleanup-4.6-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add missing of_node_put()
Inotify does not handle sysfs events, so use poll instead.
The loopback kernel driver will send a notification when the test is
complete. So, open a poll file descriptor for every enabled device,
and after starting the test, wait for an event from each device.
After all events are received, read the total number of iterations
and make sure the test is complete.
Also, add missing stdint header which was included in inotify.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Currently, user space is notified for every message sent,
but this is not really needed and does not work in the async case
where all messages are sent from the start.
Instead, notify userspace only when all the transfers are complete.
This allows userspace to wait in a poll loop and wakeup only when
the test is finished.
Also, don't use the bundle kobj to send the notification it is
the loopback device that contains the loopback attributes.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
WARN_ON() is a bit harsh here, as we just failed to power-off the HID
device while it is getting removed.
Replace it with dev_err().
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Johan Hovold <johan@hovoldconsulting.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
hid_destroy_device() can potentially call callbacks defined in struct
hid_ll_driver, which may initiate few greybus operations.
And so connection (tx) should be kept enabled until the hid-device isn't
destroyed.
Reported-by: Jiss Kuruvila <jkuruvila@google.com>
Reported-by: Laurent Pinchart <laurent.pinchart@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Johan Hovold <johan@hovoldconsulting.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
If the block size of a filesystem is not at least PAGE_SIZEd, then
at this point in time DAX cannot be used due to the fact we can't
guarantee extents are page sized or aligned without further work.
Hence disallow setting the DAX flag on an inode if the block size is
too small. Also, be defensive and check the block size when reading
an inode in off disk.
In future, we want to allow DAX to work on any filesystem, so this
is temporary while we sort of the correct conbination of extent size
hints and allocation alignment configurations needed to guarantee
page sized and aligned extent allocation for DAX enabled files.
Signed-off-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Brian Foster <bfoster@redhat.com>
Tested-by: Ross Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: Dave Chinner <david@fromorbit.com>
When we set or clear the XFS_DIFLAG2_DAX flag, we should also
set/clear the S_DAX flag in the VFS inode. To do this, we need to
ensure that we first flush and remove any cached entries in the
radix tree to ensure the correct data access method is used when we
next try to read or write data. We ahve to be especially careful
here to lock out page faults so they don't race with the flush and
invalidation before we change the access mode.
Signed-off-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Brian Foster <bfoster@redhat.com>
Tested-by: Ross Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: Dave Chinner <david@fromorbit.com>
Only regular files can use DAX for data operations, so we should
restrict setting it on the VFS inode to regular files. Setting it on
metadata inodes may cause the VFS to do the wrong thing for such
inodes, so avoid potential problems by restricting the scope of the
flag to what we know is supported.
Signed-off-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Brian Foster <bfoster@redhat.com>
Tested-by: Ross Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: Dave Chinner <david@fromorbit.com>
Only file data can use DAX, so we should onyl be able to set this
flag on regular files. However, the flag also serves as an "inherit"
flag at file create time when set on directories, so limit the
FS_IOC_FSSETXATTR ioctl to only set this flag on regular files and
directories.
Signed-off-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Brian Foster <bfoster@redhat.com>
Tested-by: Ross Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: Dave Chinner <david@fromorbit.com>
We need to finish doing the CRC checks before we can allow writes to
happen, and we currently process the inodes in order. This means a call
to jffs2_get_ino_cache() for each possible inode# up to c->highest_ino.
There may be a lot of lookups which fail, if the inode# space is used
sparsely. And the inode# space is *often* used sparsely, if a file
system contains a lot of stuff that was put there in the original
image, followed by lots of creation and deletion of new files.
Instead of processing them numerically with a lookup each time, just
walk the hash buckets instead.
[fix locking typo reported by Dan Carpenter]
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The BRCMNAND controller revision 7.1 is almost 100% compatible with the
previous v6.0 register offset layout, except for the Correctable Error
Reporting Threshold registers. Fix this by adding another table with the
correct offsets for CORR_THRESHOLD and CORR_THRESHOLD_EXT.
Fixes: 27c5b17cd1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The qcom-spmi-mpp driver is now using string "digital" to denote
old "normal" functionality. Update DTS file.
Also update the powersource.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Since the wait list is not protected against concurrent access
it must be processed from the context of the completion handler.
Replace the wait list processing code in the IB CM RTU callback
handler by code that triggers a completion handler. This patch
fixes the following rare crash:
WARNING: CPU: 2 PID: 78656 at lib/list_debug.c:53 __list_del_entry+0x67/0xd0()
list_del corruption, ffff88041ae404b8->next is LIST_POISON1 (dead000000000100)
Call Trace:
[<ffffffff81251c6b>] dump_stack+0x4f/0x74
[<ffffffff810574ab>] warn_slowpath_common+0x8b/0xd0
[<ffffffff81057591>] warn_slowpath_fmt+0x41/0x70
[<ffffffff8126f007>] __list_del_entry+0x67/0xd0
[<ffffffff8126f081>] list_del+0x11/0x40
[<ffffffffa0265242>] srpt_cm_handler+0x172/0x1a4 [ib_srpt]
[<ffffffffa0370370>] cm_process_work+0x20/0xf0 [ib_cm]
[<ffffffffa0370dae>] cm_establish_handler+0xbe/0x110 [ib_cm]
[<ffffffffa03733e7>] cm_work_handler+0x67/0xd0 [ib_cm]
[<ffffffff8107184d>] process_one_work+0x1bd/0x460
[<ffffffff81073148>] worker_thread+0x118/0x420
[<ffffffff81078444>] kthread+0xe4/0x100
[<ffffffff8151caff>] ret_from_fork+0x3f/0x70
Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Alex Estrin <alex.estrin@intel.com>
Cc: Sagi Grimberg <sagig@mellanox.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
This patch does not change any functionality.
Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Alex Estrin <alex.estrin@intel.com>
Cc: Sagi Grimberg <sagig@mellanox.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
If an initiator observes LUN deletion during shutdown of the
target stack then that will trigger an I/O error even when using
multipathd. Users need a way to avoid that shutting down the
target stack causes I/O errors, e.g. by providing a way to force
initiator logout. Hence close all sessions if a target port is
disabled.
Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Alex Estrin <alex.estrin@intel.com>
Cc: Sagi Grimberg <sagig@mellanox.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
The only allowed return values for the write_pending() callback
function are 0, -EAGAIN and -ENOMEM. Since attempting to perform
RDMA over a disconnecting channel will result in an IB error
completion anyway, remove the code that checks the channel state
from srpt_write_pending().
Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Sagi Grimberg <sagig@mellanox.com>
Cc: Alex Estrin <alex.estrin@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
The Last WQE Reached event is only generated after one or more work
requests have been queued on the QP associated with a session. Since
session shutdown can start before any work requests have been queued,
use a zero-length RDMA write to wait until a QP has been drained.
Additionally, rework the code for closing and disconnecting a session.
Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Sagi Grimberg <sagig@mellanox.com>
Cc: Alex Estrin <alex.estrin@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
In a later patch a function that can block will be called while
iterating over the rch_list. Hence protect that list with a
mutex instead of a spinlock. And since it is not allowed to sleep
while the task state != TASK_RUNNING, convert the list test in
srpt_ch_list_empty() into a lockless test.
Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Sagi Grimberg <sagig@mellanox.com>
Cc: Alex Estrin <alex.estrin@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
To make it possible to determine why an initiator sent a REJ,
log the private data associated with the received REJ packet.
Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Sagi Grimberg <sagig@mellanox.com>
Cc: Alex Estrin <alex.estrin@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
