Commit graph

982,081 commits

Author SHA1 Message Date
Alexandre Torgue
48c7181fa7 ARM: dts: stm32: Update stm32mp157 pinctrl files
In order to cover the STM32MP15 SOCs family this commit updates pinctrl
file names (group definition and packages files).
This family includes: STM32MP151, STM32MP153 and STM32MP157.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Alexandre Torgue
92d3a35c07 ARM: dts: stm32: Adapt stm32mp157 pinctrl to manage STM32MP15xx SOCs family
This commit modifies stm32mp157 pinctrl files to better manage STM32MP15xx
SOCs diversity. Pin controller and gpio controller are moved to common SOC
dtsi file. Only pin groups remain in the main pinctrl dtsi file.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Benjamin Gaignard
ac4533a816 ARM: dts: stm32: remove unused rng interrupt on stm32f429
Interrupt has never be used in rng driver so remove it from DT.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Fabrice Gasnier
91ad4af4b2 ARM: dts: stm32: add ADC support to stm32mp157c-ed1
Add ADC support to stm32mp157c-ed1 board.
Following ADC signals are dedicated for analog and routed to connectors:
- ADC1/2 in0 (ANA0)
- ADC1/2 in1 (ANA1)
- ADC1 in6 (PF12)
Configure ADC1 with these signals. But keep it disabled by default, so
PF12 can be used as gpio by default.
Add VDD and VDDA supplies to ADC on stm32mp157c-ed1 board. This allows to
get full ADC analog performances in case VDDA is below 2.7V (not the case
by default).

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Fabrice Gasnier
ee39d8a3e4 ARM: dts: stm32: add ADC pins used for stm32mp157c-ed1
Define adc1_in6 pin used on stm32mp157c eval board.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Yann Gautier
7e5d839819 ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards
On STM32MP1 EVAL and DISCOVERY boards, the SDMMC3 internal peripheral
can be used through the GPIO extension connector. The sdmmc3 node is then
added in the boards DT files, and the required pins are also added.
The node status is disabled as there is no device connected by default.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-12-09 09:19:15 +01:00
Yann Gautier
0382bf82fe ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 board
On STM32MP157C-ED1, the eMMC is connected on instance 2 of SDMMC
peripheral. The sdmmc2 node is then added in the board DT file, as well as
the pins nodes in the pinctrl file.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Yann Gautier
64e11cb783 ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC
The STM32MP157 SoC series includes 3 instances of the SDMMC peripheral.
The sdmmc2 and sdmmc3 nodes are added in STM32MP157 SoC DT file.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Yann Gautier
0a1732cf6c ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157
Relax sdmmc1 pins slew-rate to minimize peak currents.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Fabrice Gasnier
f9b9aaaa06 ARM: dts: stm32: add timers counter support on stm32mp157c
Add counter support on stm32mp157c that provides quadrature encoder on
timers 1, 2, 3, 4, 5 and 8.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Fabrice Gasnier
4edf4c656d ARM: dts: stm32: add support for PWM on stm32mp157a-dk1
Add PWM support on stm32mp157a-dk1 board. There are several timers channels
made available on GPIO expansion and arduino connectors:
- Add PWM and trigger support (these timers can also be used as trigger
  for ADC).
It's easier then to configure them all. But keep them disabled by default,
so the pins are kept in their initial state to lower power consumption.
This way they can also be used as GPIO.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Fabrice Gasnier
08af740150 ARM: dts: stm32: add pwm sleep pins to stm32mp157c-ev1
Add pinctrl sleep state for PWM on stm32mp157c-ev1 board.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Fabrice Gasnier
1e381a657a ARM: dts: stm32: add pwm pin muxing for stm32mp157a-dk1
Add all PWM pinctrl definitions that can be used on stm32mp157a-dk1 board.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Fabrice Gasnier
f7a3b40baf ARM: dts: stm32: add pwm sleep pin muxing for stm32mp157c-ev1
Add PWM pinctrl definitions used in low-power (sleep) mode on
stm32mp157c-ev1.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09 09:19:15 +01:00
Yunhao Tian
4ff40d140e
clk: sunxi-ng: v3s: Fix incorrect number of hw_clks.
The hws field of sun8i_v3s_hw_clks has only 74
members. However, the number specified by CLK_NUMBER
is 77 (= CLK_I2S0 + 1). This leads to runtime segmentation
fault that is not always reproducible.

This patch fixes the problem by specifying correct clock number.

Signed-off-by: Yunhao Tian <18373444@buaa.edu.cn>
[Maxime: Also remove the CLK_NUMBER definition]
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-09 08:49:31 +01:00
Lucas Stach
fcb1991c46 arm64: dts: imx8mq: add missing SAI nodes
Currently only SAI2 is present in the DT. Add all the other SAI
instances present on the SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 15:49:07 +08:00
Corentin Labbe
5d22a61882
clk: sunxi: use of_device_get_match_data
The usage of of_device_get_match_data reduce the code size a bit.

Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-09 08:49:02 +01:00
Clément Péron
59f3f4dcf6
arm64: dts: allwinner: h6: Enable USB 3.0 host for Beelink GS1 and Tanix TX6
Enable USB 3.0 phy and host controller.

VBUS is directly connected to DCIN 5V and doesn't
require to be switched on.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-09 08:47:15 +01:00
Andre Heider
2c63afdafa
arm64: dts: allwinner: orange-pi-3: Enable IR receiver
Orange Pi 3 has an on-board IR receiver, enable it.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-09 08:47:15 +01:00
Stefan Mavrodiev
3d615c2fc2
arm64: dts: allwinner: a64: olinuxino: Fix SDIO supply regulator
A64-OLinuXino uses DCDC1 (VCC-IO) for MMC1 supply. In commit 916b68cfe4
("arm64: dts: a64-olinuxino: Enable RTL8723BS WiFi") ALDO2 is set, which is
VCC-PL. Since DCDC1 is always present, the boards are working without a
problem.

This patch sets the correct regulator.

Fixes: 916b68cfe4 ("arm64: dts: a64-olinuxino: Enable RTL8723BS WiFi")
Cc: stable@vger.kernel.org # v4.16+
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-09 08:46:59 +01:00
Stefan Mavrodiev
8467ebbf70
arm64: dts: allwinner: a64: olinuxino: Fix eMMC supply regulator
A64-OLinuXino-eMMC uses 1.8V for eMMC supply. This is done via a triple
jumper, which sets VCC-PL to either 1.8V or 3.3V. This setting is different
for boards with and without eMMC.

This is not a big issue for DDR52 mode, however the eMMC will not work in
HS200/HS400, since these modes explicitly requires 1.8V.

Fixes: 94f68f3a4b ("arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)")
Cc: stable@vger.kernel.org # v5.4
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-09 08:46:59 +01:00
Martin Blumenstingl
43cb86799f drm: meson: venc: cvbs: fix CVBS mode matching
With commit 222ec1618c ("drm: Add aspect ratio parsing in DRM
layer") the drm core started honoring the picture_aspect_ratio field
when comparing two drm_display_modes. Prior to that it was ignored.
When the CVBS encoder driver was initially submitted there was no aspect
ratio check.

Switch from drm_mode_equal() to drm_mode_match() without
DRM_MODE_MATCH_ASPECT_RATIO to fix "kmscube" and X.org output using the
CVBS connector. When (for example) kmscube sets the output mode when
using the CVBS connector it passes HDMI_PICTURE_ASPECT_NONE, making the
drm_mode_equal() fail as it include the aspect ratio.

Prior to this patch kmscube reported:
  failed to set mode: Invalid argument

The CVBS mode checking in the sun4i (drivers/gpu/drm/sun4i/sun4i_tv.c
sun4i_tv_mode_to_drm_mode) and ZTE (drivers/gpu/drm/zte/zx_tvenc.c
tvenc_mode_{pal,ntsc}) drivers don't set the "picture_aspect_ratio" at
all. The Meson VPU driver does not rely on the aspect ratio for the CVBS
output so we can safely decouple it from the hdmi_picture_aspect
setting.

Cc: <stable@vger.kernel.org>
Fixes: 222ec1618c ("drm: Add aspect ratio parsing in DRM layer")
Fixes: bbbe775ec5 ("drm: Add support for Amlogic Meson Graphic Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: squashed with drm: meson: venc: cvbs: deduplicate the meson_cvbs_mode lookup code]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191208171832.1064772-3-martin.blumenstingl@googlemail.com
2019-12-09 08:30:13 +01:00
Ruslan V. Sushko
4999236e05 arm64: dts: zii-ultra: adjust board names
Change ZII Ultra board names to be more in line with other ZII RDU platforms.

Signed-off-by: Ruslan Sushko <Ruslan.Sushko@zii.aero>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 15:27:18 +08:00
Lucas Stach
cd262dbfd7 soc: imx8: print SoC type and revision
This is useful information to have when looking through system logs,
so add it to the output.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 15:20:55 +08:00
Dave Airlie
781d5eb4b4 - A fix for a memory leak in the dma-buf support
- One in mcde DSI support that leads to a pointer dereference
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 xQsBAP0QPvSRo5KwRLFt/yzJYkymmG7VsHC494Bc/mVqMhesTQD/YXlH6msZLpWY
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Merge tag 'drm-misc-fixes-2019-11-25' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes

 - A fix for a memory leak in the dma-buf support
 - One in mcde DSI support that leads to a pointer dereference

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20191125094336.GA14723@gilmour.lan
2019-12-09 17:13:19 +10:00
Guido Günther
1987ddfca3 arm64: dts: imx8mq: Add eLCDIF controller
Add a node for the eLCDIF controller, "disabled" by default.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 15:12:31 +08:00
Takashi Sakamoto
9ff3483e5c ALSA: firewire-motu: fix double unlocked 'motu->mutex'
Mutex is doubly unlocked in some error path of pcm.open. This commit fixes
ALSA firewire-motu driver in Linux kernel v5.5.

Reported-by: kbuild test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: 3fd80b2003 ("ALSA: firewire-motu: use the same size of period for PCM substream in AMDTP streams")
Fixes: 0f5482e787 ("ALSA: firewire-motu: share PCM buffer size for both direction")
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Link: https://lore.kernel.org/r/20191208232226.6685-1-o-takashi@sakamocchi.jp
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-12-09 07:55:45 +01:00
Philipp Zabel
912b9dacf3 arm64: dts: imx8mq: increase NOC clock to 800 MHz
The NOC clock defaults to 400 MHz. Increase it to 800 MHz for improved
memory performance.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 14:19:37 +08:00
Kefeng Wang
bc3e8f5d42 riscv: only select serial sifive if TTY is enabled
There is some warning if TTY is not enabled, and lead to
build error, only select serial sifive if TTY enabled, and
this also makes randconfig happy.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
[paul.walmsley@sifive.com: updated to apply]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-12-08 20:29:01 -08:00
Olof Johansson
0e72a2f9c1 riscv: Fix build dependency for loader
The Makefile addition for the flat image loader missed an obj prefix.

For most parallel builds this worked out fine, but with -j1 the dependency
wasn't fulfilled and thus fails:

arch/riscv/boot/loader.S: Assembler messages:
arch/riscv/boot/loader.S:7: Error: file not found: arch/riscv/boot/Image

Fixes: 405fe7aa0d ("riscv: provide a flat image loader")
Cc: Christoph Hellwig <hch@lst.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-12-08 20:19:30 -08:00
Leonard Crestez
27dbc542f6 PM / devfreq: Use PM QoS for sysfs min/max_freq
Switch the handling of min_freq and max_freq from sysfs to use the
dev_pm_qos_request interface.

Since PM QoS handles frequencies as kHz this change reduces the
precision of min_freq and max_freq. This shouldn't introduce problems
because frequencies which are not an integer number of kHz are likely
not an integer number of Hz either.

Try to ensure compatibility by rounding min values down and rounding
max values up.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
[cw00.choi: Return -EAGAIN instead of -EINVAL if dev_pm_qos is inactive]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2019-12-09 12:19:16 +09:00
Leonard Crestez
05d7ae15cf PM / devfreq: Add PM QoS support
Register notifiers with the PM QoS framework in order to respond to
requests for DEV_PM_QOS_MIN_FREQUENCY and DEV_PM_QOS_MAX_FREQUENCY.

No notifiers are added by this patch but PM QoS constraints can be
imposed externally (for example from other devices).

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2019-12-09 12:19:16 +09:00
Leonard Crestez
42a6b25e67 PM / devfreq: Don't fail devfreq_dev_release if not in list
Right now devfreq_dev_release will print a warning and abort the rest of
the cleanup if the devfreq instance is not part of the global
devfreq_list. But this is a valid scenario, for example it can happen if
the governor can't be found or on any other init error that happens
after device_register.

Initialize devfreq->node to an empty list head in devfreq_add_device so
that list_del becomes a safe noop inside devfreq_dev_release and we can
continue the rest of the cleanup.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2019-12-09 12:19:16 +09:00
Leonard Crestez
46cecc0bf0 PM / devfreq: Introduce get_freq_range helper
Moving handling of min/max freq to a single function and call it from
update_devfreq and for printing min/max freq values in sysfs.

This changes the behavior of out-of-range min_freq/max_freq: clamping
is now done at evaluation time. This means that if an out-of-range
constraint is imposed by sysfs and it later becomes valid then it will
be enforced.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2019-12-09 12:19:16 +09:00
Leonard Crestez
e7cc792d00 PM / devfreq: Set scaling_max_freq to max on OPP notifier error
The devfreq_notifier_call functions will update scaling_min_freq and
scaling_max_freq when the OPP table is updated.

If fetching the maximum frequency fails then scaling_max_freq remains
set to zero which is confusing. Set to ULONG_MAX instead so we don't
need special handling for this case in other places.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2019-12-09 12:19:15 +09:00
Leonard Crestez
e876e710ed PM / devfreq: Fix devfreq_notifier_call returning errno
Notifier callbacks shouldn't return negative errno but one of the
NOTIFY_OK/DONE/BAD values.

The OPP core will ignore return values from notifiers but returning a
value that matches NOTIFY_STOP_MASK will stop the notification chain.

Fix by always returning NOTIFY_OK.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2019-12-09 12:19:15 +09:00
Peng Fan
ed11e31709 clk: imx: clk-imx7ulp: Add missing sentinel of ulp_div_table
There should be a sentinel of ulp_div_table, otherwise _get_table_div
may access data out of the array.

Fixes: b1260067ac ("clk: imx: add imx7ulp clk driver")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 10:53:45 +08:00
Leonard Crestez
2ef139393f clk: imx8m: Suppress bind attrs
The clock drivers on imx8m series are registered as platform devices and
this opens the possibility of reloading the driver at runtime.

This doesn't actually work: clocks are never removed and attempting to
bind again results in registration errors and a crash. Almost all
devices depend on clocks anyway so rebinding is unlikely to ever be
useful

Fix this by explicitly suppressing bind attrs like several other
clock drivers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 10:36:34 +08:00
Fabio Estevam
c13f370d49 clk: imx7ulp: Fix watchdog2 clock name typo
There is a typo in the watchdog2 clock name.

Fix it by changing it to "wdg2".

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 10:31:18 +08:00
Jan Remmet
3ff86050da clk: imx6q: disable non functional divider
The /2 divider between pll4_audio_div and pll4_post_div is not working
on imx6q. The frequency is not halved as reported by the clock tree
and measured on clko.
In the technical reference manual the divider was removed in revision 4.
It's also not listed in the imx6qp manual.

imx6dl manual mentions a divider for PLL4 and the according register
description. So keep the divider here.

Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 10:09:12 +08:00
Jason A. Donenfeld
e7096c131e net: WireGuard secure network tunnel
WireGuard is a layer 3 secure networking tunnel made specifically for
the kernel, that aims to be much simpler and easier to audit than IPsec.
Extensive documentation and description of the protocol and
considerations, along with formal proofs of the cryptography, are
available at:

  * https://www.wireguard.com/
  * https://www.wireguard.com/papers/wireguard.pdf

This commit implements WireGuard as a simple network device driver,
accessible in the usual RTNL way used by virtual network drivers. It
makes use of the udp_tunnel APIs, GRO, GSO, NAPI, and the usual set of
networking subsystem APIs. It has a somewhat novel multicore queueing
system designed for maximum throughput and minimal latency of encryption
operations, but it is implemented modestly using workqueues and NAPI.
Configuration is done via generic Netlink, and following a review from
the Netlink maintainer a year ago, several high profile userspace tools
have already implemented the API.

This commit also comes with several different tests, both in-kernel
tests and out-of-kernel tests based on network namespaces, taking profit
of the fact that sockets used by WireGuard intentionally stay in the
namespace the WireGuard interface was originally created, exactly like
the semantics of userspace tun devices. See wireguard.com/netns/ for
pictures and examples.

The source code is fairly short, but rather than combining everything
into a single file, WireGuard is developed as cleanly separable files,
making auditing and comprehension easier. Things are laid out as
follows:

  * noise.[ch], cookie.[ch], messages.h: These implement the bulk of the
    cryptographic aspects of the protocol, and are mostly data-only in
    nature, taking in buffers of bytes and spitting out buffers of
    bytes. They also handle reference counting for their various shared
    pieces of data, like keys and key lists.

  * ratelimiter.[ch]: Used as an integral part of cookie.[ch] for
    ratelimiting certain types of cryptographic operations in accordance
    with particular WireGuard semantics.

  * allowedips.[ch], peerlookup.[ch]: The main lookup structures of
    WireGuard, the former being trie-like with particular semantics, an
    integral part of the design of the protocol, and the latter just
    being nice helper functions around the various hashtables we use.

  * device.[ch]: Implementation of functions for the netdevice and for
    rtnl, responsible for maintaining the life of a given interface and
    wiring it up to the rest of WireGuard.

  * peer.[ch]: Each interface has a list of peers, with helper functions
    available here for creation, destruction, and reference counting.

  * socket.[ch]: Implementation of functions related to udp_socket and
    the general set of kernel socket APIs, for sending and receiving
    ciphertext UDP packets, and taking care of WireGuard-specific sticky
    socket routing semantics for the automatic roaming.

  * netlink.[ch]: Userspace API entry point for configuring WireGuard
    peers and devices. The API has been implemented by several userspace
    tools and network management utility, and the WireGuard project
    distributes the basic wg(8) tool.

  * queueing.[ch]: Shared function on the rx and tx path for handling
    the various queues used in the multicore algorithms.

  * send.c: Handles encrypting outgoing packets in parallel on
    multiple cores, before sending them in order on a single core, via
    workqueues and ring buffers. Also handles sending handshake and cookie
    messages as part of the protocol, in parallel.

  * receive.c: Handles decrypting incoming packets in parallel on
    multiple cores, before passing them off in order to be ingested via
    the rest of the networking subsystem with GRO via the typical NAPI
    poll function. Also handles receiving handshake and cookie messages
    as part of the protocol, in parallel.

  * timers.[ch]: Uses the timer wheel to implement protocol particular
    event timeouts, and gives a set of very simple event-driven entry
    point functions for callers.

  * main.c, version.h: Initialization and deinitialization of the module.

  * selftest/*.h: Runtime unit tests for some of the most security
    sensitive functions.

  * tools/testing/selftests/wireguard/netns.sh: Aforementioned testing
    script using network namespaces.

This commit aims to be as self-contained as possible, implementing
WireGuard as a standalone module not needing much special handling or
coordination from the network subsystem. I expect for future
optimizations to the network stack to positively improve WireGuard, and
vice-versa, but for the time being, this exists as intentionally
standalone.

We introduce a menu option for CONFIG_WIREGUARD, as well as providing a
verbose debug log and self-tests via CONFIG_WIREGUARD_DEBUG.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Cc: David Miller <davem@davemloft.net>
Cc: Greg KH <gregkh@linuxfoundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: netdev@vger.kernel.org
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-12-08 17:48:42 -08:00
Yongqiang Niu
92c17f6043 drm/mediatek: Fix can't get component for external display plane.
The original logic is ok for primary display, but will not find out
component for external display.

For example, plane->index is 6 for external display, but there are only
2 layer nr in external display, and this condition will never happen:
if (plane->index < (count + mtk_ddp_comp_layer_nr(comp)))

Fix this by using the offset of the plane to mtk_crtc->planes as index,
instead of plane->index.

Fixes: d6b53f6835 ("drm/mediatek: Add helper to get component for a plane")
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-12-09 09:29:05 +08:00
Pi-Hsun Shih
13b0ba33d7 drm/mediatek: Check return value of mtk_drm_ddp_comp_for_plane.
The mtk_drm_ddp_comp_for_plane can return NULL, but the usage doesn't
check for it. Add check for it.

Fixes: d6b53f6835 ("drm/mediatek: Add helper to get component for a plane")
Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-12-09 09:29:05 +08:00
Leonard Crestez
0376f6ec9e arm64: dts: imx8m: Add ddr controller nodes
This is used by the imx-ddrc devfreq driver to implement dynamic
frequency scaling of DRAM.

Support for proactive scaling via interconnect will come later. The
high-performance bus masters which need that (display, vpu, gpu) are
mostly not yet enabled in upstream anyway.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 09:22:26 +08:00
Leonard Crestez
e18f64712e clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE
DRAM frequency switches are executed in firmware and can change the
configuration of the DRAM PLL outside linux. Mark these CLKs with
CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and
recalculate rates.

In current DRAM frequency tables on 8mm/8mn only the maximum frequency
uses the PLL so it's always configured in the same way. However reading
back the PLL configuration is the correct behavior and allows additional
setpoints in the future.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 09:15:26 +08:00
Leonard Crestez
d9ea9ca2b4 clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks
These clocks are only modified as part of DRAM frequency switches during
which DRAM itself is briefly inaccessible. The switch is performed with
a SMC call to by TF-A which runs from a SRAM area; upon returning to
linux several clocks bits are modified and we need to update them.

For rate bits an easy solution is to just mark with
CLK_GET_RATE_NOCACHE so that new rates are always read back from
registers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 09:15:12 +08:00
Masahiro Yamada
cf6b58ab2d kbuild: fix 'No such file or directory' warning when cleaning
Since commit fcbb8461fd ("kbuild: remove header compile test"),
'make clean' with O= option in the pristine source tree emits
'No such file or directory' warning.

$ git clean -d -f -x
$ make O=foo clean
make[1]: Entering directory '/home/masahiro/linux/foo'
find: ‘usr/include’: No such file or directory
make[1]: Leaving directory '/home/masahiro/linux/foo'

Fixes: fcbb8461fd ("kbuild: remove header compile test")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2019-12-09 10:08:21 +09:00
Andreas Kemnade
b731fadff4 ARM: dts: e60k02: fix power button
The power button was only producing irqs, but no key events,
Forced power down with long key press works, so probably
only a short spike arrives at the SoC.
Further investigation shows that LDORTC2 is off after boot
of the vendor kernel. LDORTC2 is shared with a GPIO at the pmic
which probably transfers the button press to the SoC.
That regulator off at boot, so "regulator-boot-on" is definitively
wrong. So remove that.

Reported-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Fixes: c100ea86e6 ("ARM: dts: add Netronix E60K02 board common file")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 08:55:16 +08:00
Fancy Fang
0f93eb28ff arm64: dts: imx8mn: remove "simple-bus" for anatop
Remove "simple-bus" compatible for device anatop,
since no child nodes exist under it and it is not
a populated bus.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 08:28:52 +08:00
Fancy Fang
0900a48492 arm64: dts: imx8mm: remove "simple-bus" for anatop
Remove "simple-bus" compatible for device anatop,
since no child nodes exist under it and it is not
a populated bus.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09 08:28:51 +08:00