- Fix the layering violation in the use of the EFI runtime services
availability mask in users of the 'efivars' abstraction
- Revert build fix for GCC v4.8 which is no longer supported
- Some fixes for build issues found by Atish while working on RISC-V support
- Avoid --whole-archive when linking the stub on arm64
- Some x86 EFI stub cleanups from Arvind
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEEnNKg2mrY9zMBdeK7wjcgfpV0+n0FAl8GytsACgkQwjcgfpV0
+n14mAgAv2997kOXLeVeMVqAkClBjQRckIFXojVzILeO228Qb3NzKFsdY9m5x7nZ
FqZyd8Vmw2LywJuyEAhHMNF8pBFzSATo2XGuvNXEIYDXNO0noOBu5eBrcAe5cTa/
grBu1WynVHwcIZefpGF0rtEp1mv5waYGcUYaeFK/cKtL57rK8TpS7XRQiRFgFamT
K8CgjCYuk6FjenMChDhbyD33QKKu3P7Xm1uxiZOOR/O2iisqYdQm/6hzKwduOvRr
ctT4pdjsi4VVC9VE09BYHvQtUpCwXKqVyd5WDwX20wfMQwiho276t2wNhaw5QkYD
w2hYBAx3TiYjJ0yFrd+Dd+CjQKX6jw==
=sl06
-----END PGP SIGNATURE-----
Merge tag 'efi-urgent-for-v5.8-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into efi/urgent
Pull EFI fixes from Ard Biesheuvel:
- Fix the layering violation in the use of the EFI runtime services
availability mask in users of the 'efivars' abstraction
- Revert build fix for GCC v4.8 which is no longer supported
- Some fixes for build issues found by Atish while working on RISC-V support
- Avoid --whole-archive when linking the stub on arm64
- Some x86 EFI stub cleanups from Arvind
drm_atomic_crtc_check enforces that ::active can only be true if
::enable is as well.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
It's not necessary to retrieve the power features status when the
asic is booted up the first time. This patch can have the features
enablement status still checked in suspend/resume case and removed
from the first boot up sequence.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fix this warning:
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h:29,
from drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h:26,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:43,
from drivers/gpu/drm/amd/amdgpu/df_v3_6.c:23:
drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function ‘df_v3_6_pmc_get_count’:
./include/drm/drm_print.h:487:2: warning: ‘hi_base_addr’ may be used uninitialized in this function [-Wmaybe-uninitialized]
487 | __drm_dbg(DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/df_v3_6.c:649:25: note: ‘hi_base_addr’ was declared here
649 | uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
| ^~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h:29,
from drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h:26,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:43,
from drivers/gpu/drm/amd/amdgpu/df_v3_6.c:23:
./include/drm/drm_print.h:487:2: warning: ‘lo_base_addr’ may be used uninitialized in this function [-Wmaybe-uninitialized]
487 | __drm_dbg(DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/df_v3_6.c:649:11: note: ‘lo_base_addr’ was declared here
649 | uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
All gc/mmhub register access and operation should be in gfxhub/mmhub level.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This patch is to move get_invalidate_req into gfxhub/mmhub level. It will avoid
mismatch of the different gfxhub/mmhub register offsets and fields in the same
gmc block.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This patch is to introduce vmhub funcs helper to add following callback
(print_l2_protection_fault_status). Each GC/MMHUB register specific programming
should be in gfxhub/mmhub level.
v2: remove the condition of funcs assignment.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This patch is to add set_vm_fault_masks helper to amdgpu_gmc to refine the
original programming.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This patch adds a member in vmhub structure to store the vm fault interrupt
masks for different version gfxhubs/mmhubs.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The below 3 messages are not supported on Renoir
SMU_MSG_PrepareMp1ForShutdown
SMU_MSG_PrepareMp1ForUnload
SMU_MSG_PrepareMp1ForReset
It needs to revert patch:
drm/amd/powerplay: drop unnecessary message support check
to avoid set mp1 state fail during gpu reset on renoir.
Signed-off-by: changfeng <Changfeng.Zhu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This will tell users if the faulty page has been written to
external eeprom device in dmesg log.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Commit 711419e504 ("irqdomain: Add the missing assignment of
domain->fwnode for named fwnode") unintentionally caused a dangling pointer
page fault issue on firmware nodes that were freed after IRQ domain
allocation. Commit e3beca48a4 fixed that dangling pointer issue by only
freeing the firmware node after an IRQ domain allocation failure. That fix
no longer frees the firmware node immediately, but leaves the firmware node
allocated after the domain is removed.
The firmware node must be kept around through irq_domain_remove, but should be
freed it afterwards.
Add the missing free operations after domain removal where where appropriate.
Fixes: e3beca48a4 ("irqdomain/treewide: Keep firmware node unconditionally allocated")
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # drivers/pci
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/1595363169-7157-1-git-send-email-jonathan.derrick@intel.com
show_trace_log_lvl() provides x86 platform-specific way to unwind
backtrace with a given log level. Unfortunately, registers dump(s) are
not printed with the same log level - instead, KERN_DEFAULT is always
used.
Arista's switches uses quite common setup with rsyslog, where only
urgent messages goes to console (console_log_level=KERN_ERR), everything
else goes into /var/log/ as the console baud-rate often is indecently
slow (9600 bps).
Backtrace dumps without registers printed have proven to be as useful as
morning standups. Furthermore, in order to introduce KERN_UNSUPPRESSED
(which I believe is still the most elegant way to fix raciness of sysrq[1])
the log level should be passed down the stack to register dumping
functions. Besides, there is a potential use-case for printing traces
with KERN_DEBUG level [2] (where registers dump shouldn't appear with
higher log level).
After all preparations are done, provide log_lvl parameter for
show_regs_if_on_stack() and wire up to actual log level used as
an argument for show_trace_log_lvl().
[1]: https://lore.kernel.org/lkml/20190528002412.1625-1-dima@arista.com/
[2]: https://lore.kernel.org/linux-doc/20190724170249.9644-1-dima@arista.com/
Signed-off-by: Dmitry Safonov <dima@arista.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Petr Mladek <pmladek@suse.com>
Link: https://lkml.kernel.org/r/20200629144847.492794-4-dima@arista.com
show_trace_log_lvl() provides x86 platform-specific way to unwind
backtrace with a given log level. Unfortunately, registers dump(s) are
not printed with the same log level - instead, KERN_DEFAULT is always
used.
Arista's switches uses quite common setup with rsyslog, where only
urgent messages goes to console (console_log_level=KERN_ERR), everything
else goes into /var/log/ as the console baud-rate often is indecently
slow (9600 bps).
Backtrace dumps without registers printed have proven to be as useful as
morning standups. Furthermore, in order to introduce KERN_UNSUPPRESSED
(which I believe is still the most elegant way to fix raciness of sysrq[1])
the log level should be passed down the stack to register dumping
functions. Besides, there is a potential use-case for printing traces
with KERN_DEBUG level [2] (where registers dump shouldn't appear with
higher log level).
Add log_lvl parameter to __show_regs().
Keep the used log level intact to separate visible change.
[1]: https://lore.kernel.org/lkml/20190528002412.1625-1-dima@arista.com/
[2]: https://lore.kernel.org/linux-doc/20190724170249.9644-1-dima@arista.com/
Signed-off-by: Dmitry Safonov <dima@arista.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Petr Mladek <pmladek@suse.com>
Link: https://lkml.kernel.org/r/20200629144847.492794-3-dima@arista.com
show_trace_log_lvl() provides x86 platform-specific way to unwind
backtrace with a given log level. Unfortunately, registers dump(s) are
not printed with the same log level - instead, KERN_DEFAULT is always
used.
Arista's switches uses quite common setup with rsyslog, where only
urgent messages goes to console (console_log_level=KERN_ERR), everything
else goes into /var/log/ as the console baud-rate often is indecently
slow (9600 bps).
Backtrace dumps without registers printed have proven to be as useful as
morning standups. Furthermore, in order to introduce KERN_UNSUPPRESSED
(which I believe is still the most elegant way to fix raciness of sysrq[1])
the log level should be passed down the stack to register dumping
functions. Besides, there is a potential use-case for printing traces
with KERN_DEBUG level [2] (where registers dump shouldn't appear with
higher log level).
Add log_lvl parameter to show_iret_regs() as a preparation to add it
to __show_regs() and show_regs_if_on_stack().
[1]: https://lore.kernel.org/lkml/20190528002412.1625-1-dima@arista.com/
[2]: https://lore.kernel.org/linux-doc/20190724170249.9644-1-dima@arista.com/
Signed-off-by: Dmitry Safonov <dima@arista.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Petr Mladek <pmladek@suse.com>
Link: https://lkml.kernel.org/r/20200629144847.492794-2-dima@arista.com
H.J. reported that post 5.7 a segfault of a user space task does not longer
dump the Code bytes when /proc/sys/debug/exception-trace is enabled. It
prints 'Code: Bad RIP value.' instead.
This was broken by a recent change which made probe_kernel_read() reject
non-kernel addresses.
Update show_opcodes() so it retrieves user space opcodes via
copy_from_user_nmi().
Fixes: 98a23609b1 ("maccess: always use strict semantics for probe_kernel_read")
Reported-by: H.J. Lu <hjl.tools@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/87h7tz306w.fsf@nanos.tec.linutronix.de
If a user task's stack is empty, or if it only has user regs, ORC
reports it as a reliable empty stack. But arch_stack_walk_reliable()
incorrectly treats it as unreliable.
That happens because the only success path for user tasks is inside the
loop, which only iterates on non-empty stacks. Generally, a user task
must end in a user regs frame, but an empty stack is an exception to
that rule.
Thanks to commit 71c9582528 ("x86/unwind/orc: Fix error handling in
__unwind_start()"), unwind_start() now sets state->error appropriately.
So now for both ORC and FP unwinders, unwind_done() and !unwind_error()
always means the end of the stack was successfully reached. So the
success path for kthreads is no longer needed -- it can also be used for
empty user tasks.
Reported-by: Wang ShaoBo <bobo.shaobowang@huawei.com>
Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Wang ShaoBo <bobo.shaobowang@huawei.com>
Link: https://lkml.kernel.org/r/f136a4e5f019219cbc4f4da33b30c2f44fa65b84.1594994374.git.jpoimboe@redhat.com
The ORC unwinder fails to unwind newly forked tasks which haven't yet
run on the CPU. It correctly reads the 'ret_from_fork' instruction
pointer from the stack, but it incorrectly interprets that value as a
call stack address rather than a "signal" one, so the address gets
incorrectly decremented in the call to orc_find(), resulting in bad ORC
data.
Fix it by forcing 'ret_from_fork' frames to be signal frames.
Reported-by: Wang ShaoBo <bobo.shaobowang@huawei.com>
Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Wang ShaoBo <bobo.shaobowang@huawei.com>
Link: https://lkml.kernel.org/r/f91a8778dde8aae7f71884b5df2b16d552040441.1594994374.git.jpoimboe@redhat.com
We hold the cl_lock here, and that's enough to keep stateid's from going
away, but it's not enough to prevent the files they point to from going
away. Take fi_lock and a reference and check for NULL, as we do in
other code.
Reported-by: NeilBrown <neilb@suse.de>
Fixes: 78599c42ae ("nfsd4: add file to display list of client's opens")
Reviewed-by: NeilBrown <neilb@suse.de>
Signed-off-by: J. Bruce Fields <bfields@redhat.com>
pcie_clear_device_status() resets the error bits in the PCIe Device Status
Register (PCI_EXP_DEVSTA).
Previously we did this unconditionally, but on ACPI systems, the _OSC AER
bit negotiates control of the AER capability. Per sec 4.5.1 of the System
Firmware Intermediary _OSC and DPC Updates ECN [1], this bit also covers
other error enable/status bits including the following:
Correctable Error Reporting Enable
Non-Fatal Error Reporting Enable
Fatal Error Reporting Enable
Unsupported Request Reporting Enable
These bits are all in the PCIe Device Control register (the ECN omitted
"Reporting", but I think that's a typo), so by implication the _OSC AER bit
also applies to the error status bits in the PCIe Device Status register:
Correctable Error Detected
Non-Fatal Error Detected
Fatal Error Detected
Unsupported Request Detected
Clear the PCIe Device Status error bits only when the OS controls the AER
capability and related error enable/status bits. If platform firmware
controls the AER capability, firmware is responsible for clearing these
bits.
One call path leading here is:
ghes_do_proc
ghes_handle_aer
aer_recover_queue
schedule_work(&aer_recover_work)
...
aer_recover_work_func
pcie_do_recovery
pcie_clear_device_status
[1] System Firmware Intermediary (SFI) _OSC and DPC Updates ECN, Feb 24,
2020, affecting PCI Firmware Specification, Rev. 3.2
https://members.pcisig.com/wg/PCI-SIG/document/14076
[bhelgaas: commit log, move test from pcie_clear_device_status() to callers]
Link: https://lore.kernel.org/r/20200622113523.891666-1-Jonathan.Cameron@huawei.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
pci_aer_clear_device_status() clears the error bits in the PCIe Device
Status Register (PCI_EXP_DEVSTA). Every PCIe device has this register,
regardless of whether it supports AER.
Rename pci_aer_clear_device_status() to pcie_clear_device_status() to make
clear that it is PCIe-specific but not AER-specific. Move it to
drivers/pci/pci.c, again since it's not AER-specific. No functional change
intended.
Link: https://lore.kernel.org/r/20200717195619.766662-1-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
For RPMh this fixes an issue where ktime was used during suspend, allows
the driver to be used on ARM targets and some minor cleanups.
It adds support for the latest format version in the socinfo driver and
adds identifiers for SM8250 and SDM630.
SMD-RPM gains compatibles for MSM8994 and MSM8936 and the Qualcomm SCM
gains compatibles MSM8994 and IPQ8074.
The GENI core code gains interconnect path voting and performance level
support, with subsequent patches integrating this with the SPI, I2C,
UART and QSPI drivers.
Following this the KGDB support for the GENI serial driver is improved,
the performance related to chip-select is improved for SPI and QSPI.
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAl8WWfsbHGJqb3JuLmFu
ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FNB4QAJlOgboPQpxReZ8iJUr7
C5nyBQEa6jG2HNXKyHA/OKcpuU6kchSqzoU0N7RfsuISrA6RAeBdSc8duQkWFF2u
pqhbx5KCT5hqeU0rTNtSkKLaJUg+8s3hbnKzvQmBi+GbFUM9Davs1TdT+XpeNRX+
F9Oly7Wr4LiMA1QHy+hDPLFvQzGtrIkkgvOGXxCiIeC+p3WwlNPltKkaEo/HUirL
iIhibNwWwHLhBA5pXSew5fnzU7dOU1vsOR4F7Y1mfFP2C4vvDRzEeitcutr/dLYw
r8ptzvJUwsF2gaSaSE51Ki3ToyNrVhBw9YF00/wLcidBuvXell/VO37J7WWzMpEA
Iu1Qok+KBo03TmDOpj8nreljCewQv3H3zb0PD/RIRWU5XN7UFckvc+iA0n1m5rXE
fb0FSYfIZXHRlZCi0xr1cUD/IYXynCYFQ3p+rme8dvlaaxf3wt9jclNXnqXRBb1l
LUpC33ogD4a6lJypbnz9UjNU+3Ek7nJPoi0OfwOHmVuiOBlMOu7F6kdz5t8tM25m
K6RHWsMM2M3EsI/YGL3lGQU9EBu0r8tvkDs+JfLodrG6yoISXfUCz52XpvC3UX86
HBs0NsN47nPmbRk7WrOee/NQn0t1bW8mC7hk6SkoZ6jp4i8SKyuHeCiVXQWbKHaw
Os2m2MWfrrdnRE4O42BzEeX7
=Os4F
-----END PGP SIGNATURE-----
Merge tag 'qcom-drivers-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for v5.9
For RPMh this fixes an issue where ktime was used during suspend, allows
the driver to be used on ARM targets and some minor cleanups.
It adds support for the latest format version in the socinfo driver and
adds identifiers for SM8250 and SDM630.
SMD-RPM gains compatibles for MSM8994 and MSM8936 and the Qualcomm SCM
gains compatibles MSM8994 and IPQ8074.
The GENI core code gains interconnect path voting and performance level
support, with subsequent patches integrating this with the SPI, I2C,
UART and QSPI drivers.
Following this the KGDB support for the GENI serial driver is improved,
the performance related to chip-select is improved for SPI and QSPI.
* tag 'qcom-drivers-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (35 commits)
soc: qcom: geni: Fix NULL pointer dereference
tty: serial: qcom-geni-serial: Drop the icc bw votes in suspend for console
serial: qcom_geni_serial: Always use 4 bytes per TX FIFO word
serial: qcom_geni_serial: Make kgdb work even if UART isn't console
spi: spi-geni-qcom: Get rid of most overhead in prepare_message()
spi: spi-geni-qcom: Set the clock properly at runtime resume
spi: spi-geni-qcom: Avoid clock setting if not needed
spi: spi-qcom-qspi: Set an autosuspend delay of 250 ms
spi: spi-qcom-qspi: Avoid clock setting if not needed
spi: spi-qcom-qspi: Use OPP API to set clk/perf state
firmware: qcom_scm: Add msm8994 compatible
firmware: qcom_scm: Fix legacy convention SCM accessors
<linux/of.h>: add stub for of_get_next_parent() to fix qcom build error
dt-bindings: firmware: qcom: Add compatible for IPQ8074 SoC
spi: spi-geni-qcom: Use OPP API to set clk/perf state
tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state
spi: spi-qcom-qspi: Add interconnect support
spi: spi-geni-qcom: Add interconnect support
spi: spi-geni-qcom: Combine the clock setting code
tty: serial: qcom_geni_serial: Add interconnect support
...
Link: https://lore.kernel.org/r/20200721044812.3429652-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Update SCU irq code to call pm_system_wakeup() in general MU IRQ
handler, so that system can be waked up when MU IRQ arrives.
- Move i.MX SCU soc driver into imx firmware folder to get it
initialized from i.MX SCU firmware driver.
- Clean up soc-imx-scu driver a bit by using devm_kasprintf().
- Correct postfix setting for cm40 power domain in scu-pd driver.
- Add resource management support for IMX_SCU firmware driver.
- Add more cm4 resources to i.MX SCU power domain driver.
- Select ARM_GIC_V3 from SOC_IMX8M for being able to use GICv3 driver
in AARCH32 mode Linux on AARCH64 hardware.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl8VPiUUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM5L9wf/VY0Q2oZ+gaJRNhSfVSf7O7QpscHV
mtQZPHg81jv3D2NkOpycJ1vaJEo118Ho6vb5IfeheChyZ2eWEJKkaPpVuhyKjPhK
B+nUmFnsTm8MTL+GKA1W7g6Gg+lJN3wT/mOITNmGMW0NID4/rse/XeM18+28nNb/
2svVyc1+4uTM5m+4i+scBCdnxgBK2H71/DQYLfDvNtZesWzas1PNN1nJh10D/PMM
X6d7AZ92c//pf5eR3wpm/JKZ+hubefBNWkrpw50pNlAASbgOogXWL1GU9q3r/VAV
9dS0dW9mIlpqlONEO+2zv9v1/RnoUypkCe/FFTUsA1bJ7ZGqhxWmrYwyfg==
=7Pd6
-----END PGP SIGNATURE-----
Merge tag 'imx-drivers-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers change for 5.9:
- Update SCU irq code to call pm_system_wakeup() in general MU IRQ
handler, so that system can be waked up when MU IRQ arrives.
- Move i.MX SCU soc driver into imx firmware folder to get it
initialized from i.MX SCU firmware driver.
- Clean up soc-imx-scu driver a bit by using devm_kasprintf().
- Correct postfix setting for cm40 power domain in scu-pd driver.
- Add resource management support for IMX_SCU firmware driver.
- Add more cm4 resources to i.MX SCU power domain driver.
- Select ARM_GIC_V3 from SOC_IMX8M for being able to use GICv3 driver
in AARCH32 mode Linux on AARCH64 hardware.
* tag 'imx-drivers-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: select ARM_GIC_V3 for i.MX8M
firmware: imx: Move i.MX SCU soc driver into imx firmware folder
firmware: imx: scu-pd: add more cm4 resources
firmware: imx: add resource management api
firmware: imx: scu-pd: fix cm40 power domain
soc: imx: scu: use devm_kasprintf
firmware: imx: make sure MU irq can wake up system from suspend mode
Link: https://lore.kernel.org/r/20200720085536.24138-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This tag moves the reset-simple header out of drivers/reset for use by
drivers outside of drivers/reset, adds a .reset() callback to
reset-simple, converts i.MX reset bindings to json-schema, fixes a
compile warning in the reset-intel-gw driver, and replaces some HTTP
links with HTTPS ones in comments.
-----BEGIN PGP SIGNATURE-----
iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXxWSARcccC56YWJlbEBw
ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwAP6AP4ld+W8CqwjEw+tkTVoCcGpE3v4
rmeEao1MtXtttiG9bAEAl2y794/zu0cXI0UEYqbhuqDYG/z8uXoBRvTGEP7UqQc=
=tScp
-----END PGP SIGNATURE-----
Merge tag 'reset-for-v5.9' of git://git.pengutronix.de/pza/linux into arm/drivers
Reset controller updates for v5.9
This tag moves the reset-simple header out of drivers/reset for use by
drivers outside of drivers/reset, adds a .reset() callback to
reset-simple, converts i.MX reset bindings to json-schema, fixes a
compile warning in the reset-intel-gw driver, and replaces some HTTP
links with HTTPS ones in comments.
* tag 'reset-for-v5.9' of git://git.pengutronix.de/pza/linux:
reset: Replace HTTP links with HTTPS ones
reset: intel: fix a compile warning about REG_OFFSET redefined
dt-bindings: reset: Convert i.MX7 reset to json-schema
dt-bindings: reset: Convert i.MX reset to json-schema
reset: simple: Add reset callback
reset: Move reset-simple header out of drivers/reset
Link: https://lore.kernel.org/r/b718f052e38abbaac599d80645376b75e54aa5bd.camel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add a simple custom voltage regulator coupler for Exynos5800 SoCs, which
require coupling between "vdd_arm" and "vdd_int" regulators. This coupler
ensures that the voltage values don't go below the bootloader-selected
operation point during the boot process until the clients set their
constraints. It is achieved by assuming minimal voltage value equal to
the current value if no constraints are set. This also ensures proper
voltage balancing if any of the client driver is missing.
The balancing code comes from the regulator/core.c with the additional
logic for handling regulators without client constraints applied added.
Link: https://lore.kernel.org/r/20200721180900.13844-5-krzk@kernel.org
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Sparx5 support 9 different clock outputs. This include file has
defines for each supported clock ordinal.
Link: https://lore.kernel.org/r/20200615133242.24911-8-lars.povlsen@microchip.com
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This add the DT bindings documentation for the Sparx5 SoC DPLL clock
Link: https://lore.kernel.org/r/20200615133242.24911-7-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This add pinctrl support to the Microchip Sparx5 SoC.
Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option).
Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds support for the Microchip Sparx5 ARMv8-based SoC family of
TSN-capable gigabit switches.
Link: https://lore.kernel.org/r/20200615133242.24911-3-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds the main Sparx5 SoC DT documentation file, with information
abut the supported board types.
Link: https://lore.kernel.org/r/20200615133242.24911-2-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull MD for 5.9 from Song.
* 'md-next' of https://git.kernel.org/pub/scm/linux/kernel/git/song/md:
md/raid10: avoid deadlock on recovery.
raid: md_p.h: drop duplicated word in a comment
md-cluster: fix rmmod issue when md_cluster convert bitmap to none
md-cluster: fix safemode_delay value when converting to clustered bitmap
md/raid5: support config stripe_size by sysfs entry
md/raid5: set default stripe_size as 4096
md/raid456: convert macro STRIPE_* to RAID5_STRIPE_*
raid5: remove the meaningless check in raid5_make_request
raid5: put the comment of clear_batch_ready to the right place
raid5: call clear_batch_ready before set STRIPE_ACTIVE
md: raid10: Fix compilation warning
md: raid5: Fix compilation warning
md: raid5-cache: Remove set but unused variable
md: Fix compilation warning
This enables the audio SRAM, DMA engine, I2S interface, and codec, hooks
them together and adds a audio-graph-card instance.
It also removes the jack gpios from the gpio-keys instance, because the
audio jack driver registers an input device.
Link: https://lore.kernel.org/r/20200718205019.184927-10-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This memory is region is where the two-channel audio DMA can pump sound
samples into the SSPA's internal FIFO.
Link: https://lore.kernel.org/r/20200718205019.184927-6-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The ACGR register is at the offset of 0x1024, beyond the 4k originally
assigned to the MPMU range.
Link: https://lore.kernel.org/r/20200718205019.184927-5-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The power management unit, described by the soc_clocks node, controls the
power to the peripherals by the means of power domains with a single
cell -- the domain number.
Link: https://lore.kernel.org/r/20200718205019.184927-4-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
On the XO-1.75, this node represents a bus interface that operates in slave
mode and thus is only able to accommodate a single subnode; no address
cells are necessary.
The Documentation/devicetree/bindings/spi/spi-controller.yaml binding
prefers that we drop the property instead of setting it to zero.
This fixes a DT validation error:
arch/arm/boot/dts/mmp2-olpc-xo-1-75.dt.yaml: spi@d4037000:
{ ... } is valid under each of {'required': ['spi-slave']},
{'required': ['#address-cells']}
We also need to drop #size-cells:
arch/arm/boot/dts/mmp2-olpc-xo-1-75.dt.yaml: spi@d4037000:
'#address-cells' is a dependency of '#size-cells'
Link: https://lore.kernel.org/r/20200718205019.184927-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
mmp2-olpc-xo-1-75.dt.yaml: camera_i2c: $nodename:0:
'camera_i2c' does not match '^i2c(@.*)?'
mmp2-olpc-xo-1-75.dt.yaml: camera_i2c: 'sda-gpios' is a required property
mmp2-olpc-xo-1-75.dt.yaml: camera_i2c: 'scl-gpios' is a required property
The "gpios" property actually was documented as deprecated, but got dropped
in commit 0175ce4a58 ("dt-bindings: i2c: Convert i2c-gpio binding to
json-schema"). It's probably best kept forgotten though.
Link: https://lore.kernel.org/r/20200718205019.184927-2-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The VSC7514 is marketed as a 10-port switch, however it has 11 physical
ports (0->10) in the block diagram:
https://www.microsemi.com/product-directory/ethernet-switches/3992-vsc7514
(also in the device tree at arch/mips/boot/dts/mscc/ocelot.dtsi)
Additionally, by architecture it has one more entry in the analyzer
block, situated right after the physical ports, for the CPU port module.
This is not a physical port, it only represents a channel for frame
injection and extraction. That entry for the CPU port is at index 11 in
the analyzer.
When the register groups for QSYS_SWITCH_PORT_MODE, SYS_PORT_MODE and
SYS_PAUSE_CFG are declared to be replicated 11 times, the 11th entry in
the array of regfields is not initialized, so the CPU port module is not
initialized either.
The documentation of QSYS_SWITCH_PORT_MODE for VSC7514 also says that
this register group is replicated 12 times, so this patch is simply
reflecting that and not introducing any further inconsistency.
Fixes: 886e1387c7 ("net: mscc: ocelot: convert QSYS_SWITCH_PORT_MODE and SYS_PORT_MODE to regfields")
Fixes: 541132f096 ("net: mscc: ocelot: convert SYS_PAUSE_CFG register access to regfield")
Reported-by: Bryan Whitehead <bryan.whitehead@microchip.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Highlights:
----------
MCU part:
-Enable stmpe811 on stm32f429
-Enable l3gd20-gyro on stm32f429
-Enable panel-ilitek-9341 on stm32f429
-Fixes for yaml validation (leds, nodes names,
remove useless bindings ...)
-Add stm32xxx compatibles for syscon nodes
MPU part:
-Add support for usb role switch to dwc2
-Add stm32xxx compatibles for syscon nodes
-Update uart4 pin configuration for low power mode
used by dkx and ed1 ST boards
-Fix uart nodes ordering and uart7_pins_a comments
-Add the support of uart instances available on STM32MP157 boards:
- usart3 on stm32mp157c-ev1, stm32mp157a-dk1, and stm32mp157c-dk2
- uart7 on stm32mp157a-dk1 and stm32mp157c-dk2
- usart2 on stm32mp157c-dk2
-Configure I2C5 on stm32mp15 DK boards
-----BEGIN PGP SIGNATURE-----
iQJMBAABCgA2FiEEctl9+nxzUSUqdELdf5rJavIecIUFAl8YQ6AYHGFsZXhhbmRy
ZS50b3JndWVAc3QuY29tAAoJEH+ayWryHnCFzGsP/A+rZHA3rpQXros5WEj/PV2+
1ePtLCXHW1mkhcsPQJb3p0bziGsVI8at2DMSlpeh6Koh+U8UkzD04Md4roqVWenM
XB6R6LBMuNVn2U3n3D7wGrcbkGPHTY/6lwpuyUqcm43yT8KhK1kLOdblSdeudZw6
JPowhZVk2uUXQRBr2RDZczSVYs5nAoB6qviuUN//LHVcTh/EyRAfOsB3Mdym2kqq
9umMqTLpznae5z648TdHJnDgqi/OKAFemQaLrl43dAnrZ0WfGuOfdApdlCAXfspg
RJ7Ciheba2Gd2RGAPHEhTN3+1DWErpxk2OhrhWt6YeTggkx+3V0psub807EXpZew
K1Y2xkrzPnL1uR0sK90bYVw2o+XUn08fckm7wWCWHwMKOp7WFPjBJj+CWIePAN0g
TIriAsBusxB/tN0wJJujPDvkXkZXkxo+l2P7BmY/KiXw7hhQVBsOmK+Gat56o1Ib
EkHLxUmdn0e1pJjN8DOsIA91MekEznnQ7QcQSGVdaYJXCUq8YUfB1t3Syjg1H4Vr
3RqEgbsaOva2MOKiNZ1iNWQkmmaRAmedSn0FTeQEyHu6ZULABtDApBbiKXjL8Gqf
Iw06PYjEN45r0UeOlLaSWQIRlfnRC17isFDfT9VxCEV3R84RBm7hA6VfLDvFEgj/
tC4AWykV22sYgMRn9wOg
=ga5j
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.9, round 1
Highlights:
----------
MCU part:
-Enable stmpe811 on stm32f429
-Enable l3gd20-gyro on stm32f429
-Enable panel-ilitek-9341 on stm32f429
-Fixes for yaml validation (leds, nodes names,
remove useless bindings ...)
-Add stm32xxx compatibles for syscon nodes
MPU part:
-Add support for usb role switch to dwc2
-Add stm32xxx compatibles for syscon nodes
-Update uart4 pin configuration for low power mode
used by dkx and ed1 ST boards
-Fix uart nodes ordering and uart7_pins_a comments
-Add the support of uart instances available on STM32MP157 boards:
- usart3 on stm32mp157c-ev1, stm32mp157a-dk1, and stm32mp157c-dk2
- uart7 on stm32mp157a-dk1 and stm32mp157c-dk2
- usart2 on stm32mp157c-dk2
-Configure I2C5 on stm32mp15 DK boards
* tag 'stm32-dt-for-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (38 commits)
ARM: dts: stm32: enable usb-role-switch on USB OTG on stm32mp15xx-dkx
ARM: dts: stm32: Add compatibles for syscon for stm32mp151
ARM: dts: stm32: Add compatibles for syscon for stm32h743
ARM: dts: stm32: Add compatibles for syscon for stm32f746
ARM: dts: stm32: Add compatibles for syscon for stm32f426
dt-bindings: arm: stm32: Add compatibles for syscon nodes
ARM: dts: stm32: Fix spi4 pins in stm32mp15-pinctrl
ARM: dts: stm32: configure i2c5 support on stm32mp15xx-dkx
ARM: dts: stm32: add usart2 node to stm32mp157c-dk2
ARM: dts: stm32: add uart7 support to stm32mp15xx-dkx boards
ARM: dts: stm32: add usart3 node to stm32mp157c-ev1
ARM: dts: stm32: add usart3 node to stm32mp15xx-dkx boards
ARM: dts: stm32: add usart2, usart3 and uart7 pins in stm32mp15-pinctrl
ARM: dts: stm32: cosmetic updates in stm32mp15-pinctrl
ARM: dts: stm32: fix uart7_pins_a comments in stm32mp15-pinctrl
ARM: dts: stm32: fix uart nodes ordering in stm32mp15-pinctrl
ARM: dts: stm32: Update UART4 pin states on stm32mp15xx-dkx
ARM: dts: stm32: Update pin states for uart4 on stm32mp157c-ed1
ARM: dts: stm32: update uart4 pin configuration for low power on stm32mp157
dt-bindings: usb: dwc2: Fix issues for stm32mp15x SoC
...
Link: https://lore.kernel.org/r/8a9bb27b-fc08-126a-11f7-01354e8577e1@st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
