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1,399,042 commits

Author SHA1 Message Date
Hariprasad Kelam
314007549d octeontx2-pf: Fix ethtool support for SDP representors
The hardware supports multiple MAC types, including RPM, SDP, and LBK.
However, features such as link settings and pause frames are only available
on RPM MAC, and not supported on SDP or LBK.

This patch updates the ethtool operations logic accordingly to reflect
this behavior.

Fixes: 2f7f33a095 ("octeontx2-pf: Add representors for sdp MAC")
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2025-05-14 10:37:20 +01:00
Cosmin Tanislav
6b0cd72757
regulator: max20086: fix invalid memory access
max20086_parse_regulators_dt() calls of_regulator_match() using an
array of struct of_regulator_match allocated on the stack for the
matches argument.

of_regulator_match() calls devm_of_regulator_put_matches(), which calls
devres_alloc() to allocate a struct devm_of_regulator_matches which will
be de-allocated using devm_of_regulator_put_matches().

struct devm_of_regulator_matches is populated with the stack allocated
matches array.

If the device fails to probe, devm_of_regulator_put_matches() will be
called and will try to call of_node_put() on that stack pointer,
generating the following dmesg entries:

max20086 6-0028: Failed to read DEVICE_ID reg: -121
kobject: '\xc0$\xa5\x03' (000000002cebcb7a): is not initialized, yet
kobject_put() is being called.

Followed by a stack trace matching the call flow described above.

Switch to allocating the matches array using devm_kcalloc() to
avoid accessing the stack pointer long after it's out of scope.

This also has the advantage of allowing multiple max20086 to probe
without overriding the data stored inside the global of_regulator_match.

Fixes: bfff546aae ("regulator: Add MAX20086-MAX20089 driver")
Signed-off-by: Cosmin Tanislav <demonsingur@gmail.com>
Link: https://patch.msgid.link/20250508064947.2567255-1-demonsingur@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14 11:16:52 +02:00
Alexander Stein
74c2524a51 phy: freescale: imx8m-pcie: Simplify with dev_err_probe()
Error handling in probe() can be a bit simpler with dev_err_probe().

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Link: https://lore.kernel.org/r/20250429090152.1094243-1-alexander.stein@ew.tq-group.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 10:13:47 +01:00
André Draszik
6d0e2ada3e phy: exynos5-usbdrd: s/FIELD_PREP_CONST/FIELD_PREP where appropriate
Commit 9b6662a0f7 ("phy: exynos5-usbdrd: use GENMASK and FIELD_PREP
for Exynos5 PHY registers") added FIELD_PREP_CONST() in many cases
where FIELD_PREP() would have been more appropriate. It also switched
existing uses of FIELD_PREP() to FIELD_PREP_CONST().

FIELD_PREP() is the preferred macro to use whenever possible while
FIELD_PREP_CONST() is meant to be used in constant initialisers.

Switch (back) to FIELD_PREP().

Fixes: 7e6c2ffe6c ("phy: exynos5-usbdrd: convert some FIELD_PREP_CONST() to FIELD_PREP()")
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250429-exynos5-phy-field-prep-v1-2-39eb279a3e0e@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 10:11:40 +01:00
André Draszik
b45791d487 phy: exynos5-usbdrd: fix setting LINKSYSTEM_FLADJ on exynos7870
The code here is trying to set the FLADJ field to 0x20, so it should
clear any previous value in that field before or'ing-in the new value.

Fixes: 588d5d20ca ("phy: exynos5-usbdrd: add exynos7870 USBDRD support")
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250429-exynos5-phy-field-prep-v1-1-39eb279a3e0e@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 10:11:40 +01:00
Johan Hovold
eb7a22f830 phy: qcom: qmp-pcie: drop bogus x1e80100 qref supply
The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting
one. This also avoids the follow warning at boot:

	qcom-qmp-pcie-phy 1be0000.phy: supply vdda-qref not found, using dummy regulator

Fixes: e961ec81a3 ("phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3")
Cc: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20250429075440.19901-1-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 10:10:28 +01:00
Jan Kara
b9b410cc18 fanotify: Drop use of flex array in fanotify_fh
We use flex array 'buf' in fanotify_fh to contain the file handle
content. However the buffer is not a proper flex array. It has a
preconfigured fixed size. Furthermore if fixed size is not big enough,
we use external separately allocated buffer. Hence don't pretend buf is
a flex array since we have to use special accessors anyway and instead
just modify the accessors to do the pointer math without flex array.
This fixes warnings that flex array is not the last struct member in
fanotify_fid_event or fanotify_error_event.

Signed-off-by: Jan Kara <jack@suse.cz>
Reviewed-by: Amir Goldstein <amir73il@gmail.com>
Link: https://patch.msgid.link/20250513131745.2808-2-jack@suse.cz
2025-05-14 11:06:56 +02:00
Simon Trimmer
db13e3d58c
ALSA: hda: cs35l56: Log tuning unique identifiers during firmware load
The cs35l56 smart amplifier has some informational firmware controls
that are populated by a tuning bin file to unique values - logging these
during firmware load identifies the specific configuration being used on
that device instance.

Signed-off-by: Simon Trimmer <simont@opensource.cirrus.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
Link: https://patch.msgid.link/2fcc0e6fc5b8669acb026bebe44a4995ac83b967.1747142267.git.simont@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14 10:57:41 +02:00
Simon Trimmer
823a036f04
ASoC: cs35l56: Log tuning unique identifiers during firmware load
The cs35l56 smart amplifier has some informational firmware controls
that are populated by a tuning bin file to unique values - logging these
during firmware load identifies the specific configuration being used on
that device instance.

Signed-off-by: Simon Trimmer <simont@opensource.cirrus.com>
Link: https://patch.msgid.link/47762a5f1ce2b178ad863c6698296aea09b72e10.1747142267.git.simont@opensource.cirrus.com
Acked-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14 10:57:40 +02:00
Gabor Juhos
65cb56d49f
spi: spi-qpic-snand: validate user/chip specific ECC properties
The driver only supports 512 bytes ECC step size and 4 bit ECC strength
at the moment, however it does not reject unsupported step/strength
configurations. Due to this, whenever the driver is used with a flash
chip which needs stronger ECC protection, the following warning is shown
in the kernel log:

  [    0.574648] spi-nand spi0.0: GigaDevice SPI NAND was found.
  [    0.635748] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
  [    0.649079] nand: WARNING: (null): the ECC used on your system is too weak compared to the one required by the NAND chip

Although the message indicates that something is wrong, but it often gets
unnoticed, which can cause serious problems. For example when the user
writes something into the flash chip despite the warning, the written data
may won't be readable by the bootloader or by the boot ROM. In the worst
case, when the attached SPI NAND chip is the boot device, the board may not
be able to boot anymore.

Also, it is not even possible to create a backup of the flash, because
reading its content results in bogus data. For example, dumping the first
page of the flash gives this:

  # hexdump -C -n 2048 /dev/mtd0
  00000000  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  00000040  0f 0f 0f 0f 0f 0f 0f 0d  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  00000050  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  000001c0  0f 0f 0f 0f ff 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  000001d0  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  00000200  0f 0f 0f 0f f5 5b ff ff  0f 0f 0f 0f 0f 0f 0f 0f  |.....[..........|
  00000210  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  000002f0  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 1f 0f 0f  |................|
  00000300  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  000003c0  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f ff 0f 0f 0f  |................|
  000003d0  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  00000400  0f 0f 0f 0f 0f 0f 0f 0f  e9 74 c9 06 f5 5b ff ff  |.........t...[..|
  00000410  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  000005d0  0f 0f 0f 0f ff 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  000005e0  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  00000600  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f c6 be 0f c3  |................|
  00000610  e9 74 c9 06 f5 5b ff ff  0f 0f 0f 0f 0f 0f 0f 0f  |.t...[..........|
  00000620  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  00000770  0f 0f 0f 0f 8f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  00000780  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  00000800
  #

Doing the same by using the downstream kernel results in different output:

  # hexdump -C -n 2048 /dev/mtd0
  00000000  0f 0f 0f 0f 0f 0f 0f 0f  0f 0f 0f 0f 0f 0f 0f 0f  |................|
  *
  00000800
  #

This patch adds some sanity checks to the code to prevent using the driver
with unsupported ECC step/strength configurations. After the change, probing
of the driver fails in such cases:

  [    0.655038] spi-nand spi0.0: GigaDevice SPI NAND was found.
  [    0.659159] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
  [    0.669138] qcom_snand 79b0000.spi: only 4 bits ECC strength is supported
  [    0.677476] nand: No suitable ECC configuration
  [    0.689909] spi-nand spi0.0: probe with driver spi-nand failed with error -95

This helps to avoid the aforementioned hassles until support for 8 bit ECC
strength gets implemented.

Fixes: 7304d19090 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://patch.msgid.link/20250501-qpic-snand-validate-ecc-v1-1-532776581a66@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14 10:56:48 +02:00
Alessandro Grassi
fb98bd0a13
spi: spi-sun4i: fix early activation
The SPI interface is activated before the CPOL setting is applied. In
that moment, the clock idles high and CS goes low. After a short delay,
CPOL and other settings are applied, which may cause the clock to change
state and idle low. This transition is not part of a clock cycle, and it
can confuse the receiving device.

To prevent this unexpected transition, activate the interface while CPOL
and the other settings are being applied.

Signed-off-by: Alessandro Grassi <alessandro.grassi@mailbox.org>
Link: https://patch.msgid.link/20250502095520.13825-1-alessandro.grassi@mailbox.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14 10:56:43 +02:00
Algea Cao
f9475055b1 phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error
When using HDMI PLL frequency division coefficient at 50.25MHz
that is calculated by rk_hdptx_phy_clk_pll_calc(), it fails to
get PHY LANE lock. Although the calculated values are within the
allowable range of PHY PLL configuration.

In order to fix the PHY LANE lock error and provide the expected
50.25MHz output, manually compute the required PHY PLL frequency
division coefficient and add it to ropll_tmds_cfg configuration
table.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250427095124.3354439-1-algea.cao@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:55:09 +01:00
Jouni Högander
a8eb102ce0 drm/i915/alpm: Stop writing ALPM registers when PSR is enabled
Currently we are seeing these on PTL:

xe 0000:00:02.0: [drm] *ERROR* Timeout waiting for DDI BUF A to get active

These seem to be caused by writing ALPM registers while Panel Replay is
enabled.

Fix this by writing ALPM registers only when Panel Replay is about to be
enabled.

v4: improve comment on intel_psr_panel_replay_enable_sink call
v3: enable/disable ALPM from PSR code

Fixes: 172757acd6 ("drm/i915/lobf: Add lobf enablement in post plane update")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250513054814.3702977-3-jouni.hogander@intel.com
2025-05-14 11:50:50 +03:00
Jouni Högander
2d27848876 drm/i915/alpm: Make intel_alpm_enable_sink available for PSR
We want to enable sink ALPM from PSR code. Make intel_alpm_enable_sink
available for PSR.

v2: do not add kerneldoc comments

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250513054814.3702977-2-jouni.hogander@intel.com
2025-05-14 11:50:49 +03:00
Wei Fang
664bf117a3 net: enetc: fix implicit declaration of function FIELD_PREP
The kernel test robot reported the following error:

drivers/net/ethernet/freescale/enetc/ntmp.c: In function 'ntmp_fill_request_hdr':
drivers/net/ethernet/freescale/enetc/ntmp.c:203:38: error: implicit
declaration of function 'FIELD_PREP' [-Wimplicit-function-declaration]
203 |         cbd->req_hdr.access_method = FIELD_PREP(NTMP_ACCESS_METHOD,
    |                                      ^~~~~~~~~~

Therefore, add "bitfield.h" to ntmp_private.h to fix this issue.

Fixes: 4701073c3d ("net: enetc: add initial netc-lib driver to support NTMP")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505101047.NTMcerZE-lkp@intel.com/
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2025-05-14 09:48:49 +01:00
Mike Looijmans
065d5885f6 phy-zynqmp: Postpone getting clock rate until actually needed
At probe time the driver would display the following error and abort:
  xilinx-psgtr fd400000.phy: Invalid rate 0 for reference clock 0

At probe time, the associated GTR driver (e.g. SATA or PCIe) hasn't
initialized the clock yet, so clk_get_rate() likely returns 0 if the clock
is programmable. So this driver only works if the clock is fixed.

The PHY driver doesn't need to know the clock frequency at probe yet, so
wait until the associated driver initializes the lane before requesting the
clock rate setting.

In addition to allowing the driver to be used with programmable clocks,
this also reduces the driver's runtime memory footprint by removing an
array of pointers from struct xpsgtr_phy.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20250428063648.22034-1-mike.looijmans@topic.nl
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:48:01 +01:00
Jiawen Wu
838b2a28c0 net: wangxun: Correct clerical errors in comments
There are wrong "#endif" comments in .h files need to be corrected.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2025-05-14 09:47:33 +01:00
Hal Feng
3f097adb9b phy: starfive: jh7110-usb: Fix USB 2.0 host occasional detection failure
JH7110 USB 2.0 host fails to detect USB 2.0 devices occasionally. With a
long time of debugging and testing, we found that setting Rx clock gating
control signal to normal power consumption mode can solve this problem.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20250422101244.51686-1-hal.feng@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:45:12 +01:00
AngeloGioacchino Del Regno
1b1e949924 dt-bindings: phy: mediatek,tphy: Add support for MT6893
Add a compatible string for the MediaTek Dimensity 1200 (MT6893)
SoC: this chip integrates a MediaTek generic T-PHY version 2.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:44:35 +01:00
AngeloGioacchino Del Regno
fe750a871d dt-bindings: phy: mediatek,dsi-phy: Add support for MT6893
Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI
PHY found in this chip is fully compatible with the one found in
the MT8183 SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:44:35 +01:00
Goran Rađenović
518e8ffa00 ARM: dts: stm32: add initial support for stm32mp157-ultra-fly-sbc board
Add support for Ultratronik's stm32mp157c fly board. This board embeds
a STM32MP157c SOC and 1GB of DDR3. Several connections are available on
this boards: 2*USB2.0, 1*USB2.0 MiniUSB, Debug UART, 1*UART, 1*USART,
SDcard, RJ45, ...

This patch enables basic support for a kernel boot - SD-card or eMMC.

Signed-off-by: Goran Rađenović <goran.radni@gmail.com>
Link: https://lore.kernel.org/r/20250508143818.2574558-5-goran.radni@gmail.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:16 +02:00
Goran Rađenović
6c9bb5f361 MAINTAINERS: Add entry for ULTRATRONIK BOARD SUPPORT
Add a new MAINTAINERS section for the ULTRATRONIK BOARD SUPPORT, covering
the stm32mp157c-ultra-fly-sbc.dts board support file.

This ensures that maintainers of this board are properly listed and can be
notified for any relevant changes.

Signed-off-by: Goran Rađenović <goran.radni@gmail.com>
Signed-off-by: Börge Strümpfel <boerge.struempfel@gmail.com>
Link: https://lore.kernel.org/r/20250508143818.2574558-4-goran.radni@gmail.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:16 +02:00
Goran Rađenović
21dc0aa4e7 dt-bindings: arm: stm32: Document Ultratronik's Fly board DT binding
This commit documents ultra-fly-sbc devicetree binding based on
STM32MP157 SoC.

Signed-off-by: Goran Rađenović <goran.radni@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250508143818.2574558-3-goran.radni@gmail.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:16 +02:00
Goran Rađenović
8605b4d36f dt-bindings: vendor-prefixes: Add Ultratronik
Ultratronik GmbH is a German electronics company:
https://www.ultratronik-ems.de/

Signed-off-by: Goran Rađenović <goran.radni@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250508143818.2574558-2-goran.radni@gmail.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:16 +02:00
Fabrice Gasnier
5e281c436e arm64: dts: st: use lptimer3 as tick broadcast source on stm32mp257f-ev1
During the low power modes the generic ARM timer is deactivated, so the
the tick broadcast is used, based on LPTIMER3 which is clocked by LSE on
STMicroelectronics boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:16 +02:00
Fabrice Gasnier
e0919bca1a arm64: dts: st: add low-power timer nodes on stm32mp251
Add low-power timer (LPTimer) support on STM32MP25 SoC.
The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a
smaller set of features (no capture/compare) channel. Still, LPTIM5 can
be used as single PWM, counter, trigger or timer.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20250429125133.1574167-7-fabrice.gasnier@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Fabrice Gasnier
3cd55c7295 arm64: defconfig: enable STM32 LP timer clockevent driver
Enable the STM32 LP timer MFD core and clockevent drivers used on
STM32MP257F-EV1 board, for PSCI OSI.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20250429125133.1574167-6-fabrice.gasnier@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Patrice Chotard
cad2492de9 arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 board
Add SPI NOR flash nor support on stm32mp257f-ev1 board.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-3-fca0fbe6d10a@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Patrice Chotard
6dabe0d862 arm64: dts: st: Add ospi port1 pinctrl entries in stm32mp25-pinctrl.dtsi
Add pinctrl entry related to OSPI's port1 in stm32mp25-pinctrl.dtsi

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-2-fca0fbe6d10a@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Patrice Chotard
849380be00 arm64: dts: st: Add OMM node on stm32mp251
Add Octo Memory Manager (OMM) entry on stm32mp251 and its two
OSPI instance.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-1-fca0fbe6d10a@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Dario Binacchi
49ba8fc6ea ARM: dts: stm32: support STM32h747i-disco board
The board includes an STM32H747XI SoC with the following resources:
 - 2 Mbytes Flash
 - 1 Mbyte SRAM
 - LCD-TFT controller
 - MIPI-DSI interface
 - FD-CAN
 - USB 2.0 high-speed/full-speed
 - Ethernet MAC
 - camera interface

Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-9-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Dario Binacchi
8e71dfe46a ARM: dts: stm32: add an extra pin map for USART1 on stm32h743
Add an additional pin map configuration for using the USART1 controller
on the stm32h743 MCU.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-8-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Dario Binacchi
47d16ab94b ARM: dts: stm32: add pin map for UART8 controller on stm32h743
Add a pin map configuration for using the UART8 controller on the
stm32h743 MCU.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-7-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Dario Binacchi
07aa43adae ARM: dts: stm32: add uart8 node for stm32h743 MCU
Add support for UART8 by applying the settings specified in the
reference manual RM0433.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-6-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Dario Binacchi
ecab3c40fa dt-bindings: clock: stm32h7: rename USART{7,8}_CK to UART{7,8}_CK
As stated in the reference manual RM0433, the STM32H743 MCU has
USART1/2/3/6, UART4/5/7/8, and LPUART1. The patches make all the clock
macros for the serial ports consistent with the documentation.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250427074404.3278732-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:15 +02:00
Dario Binacchi
cb0c6e1244 ARM: stm32: add a new SoC - STM32H747
The STM32H747 is a dual-core MCU (Cortex-M7 running up to 480 MHz +
Cortex-M4 running up to 240 MHz) containing from 1 to 2 Mbytes of Flash
memory and 1 Mbyte of internal RAM.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-4-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:14 +02:00
Dario Binacchi
815d49f61e dt-bindings: arm: stm32: add compatible for stm32h747i-disco board
The board includes an STM32H747XI SoC with the following resources:
 - 2 Mbytes Flash
 - 1 MByte SRAM
 - LCD-TFT controller
 - MIPI-DSI interface
 - FD-CAN
 - USB 2.0 high-speed/full-speed
 - Ethernet MAC
 - camera interface

Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250427074404.3278732-3-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:14 +02:00
Dario Binacchi
6a36dca437 ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phandles
Allow expanding possible configurations for the same peripheral,
consistent with the scheme adopted in Linux.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-2-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:14 +02:00
Krzysztof Kozlowski
988cca008e ARM: dts: st: stm32: Align wifi node name with bindings
Since commit 3c3606793f ("dt-bindings: wireless: bcm4329-fmac: Use
wireless-controller.yaml schema"), bindings expect 'wifi' as node name:

  stm32h750i-art-pi.dtb: bcrmf@1: $nodename:0: 'bcrmf@1' does not match '^wifi(@.*)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250424084706.105049-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:14 +02:00
Ben Wolsieffer
1d0fec6f90 ARM: dts: stm32: add low power timer on STM32F746
Add device tree node for the low power timer on the STM32F746.

Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
Link: https://lore.kernel.org/r/20250404143514.860126-1-ben.wolsieffer@hefring.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:14 +02:00
Olivier Moysan
9358c00cbc ARM: dts: stm32: add vrefint support to adc on stm32mp13
Set STM32 ADC1&2 as consumers of BSEC, to retrieve vrefint calibration
data on STM32MP13x SoCs.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Link: https://lore.kernel.org/r/20250403115954.1061528-3-olivier.moysan@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:14 +02:00
Olivier Moysan
4fa5147389 ARM: dts: stm32: add vrefint calibration on stm32mp13
Describe vrefint calibration cell to be retrieved through bsec,
on STM32MP13x SoCs family.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Link: https://lore.kernel.org/r/20250403115954.1061528-2-olivier.moysan@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14 10:36:14 +02:00
Rob Herring (Arm)
2063eedf3c dt-bindings: phy: rockchip: Convert RK3399 Type-C PHY to schema
Convert the Rockchip RK3399 Type-C PHY to DT schema format. Add the
missing "power-domains" property and "port" and "orientation-switch"
properties in the child nodes.

Omit the previously deprecated properties as they aren't used anywhere.

Drop the 2nd example which was pretty much identical to the 1st example.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250416202419.3836688-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:32:02 +01:00
Chen Ni
3b2b414927 phy: rockchip: samsung-hdptx: Remove unneeded semicolon
Remove unnecessary semicolons reported by Coccinelle/coccicheck and the
semantic patch at scripts/coccinelle/misc/semicolon.cocci.

Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
Link: https://lore.kernel.org/r/20250415081200.349939-1-nichen@iscas.ac.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:30:08 +01:00
Chenyuan Yang
d14402a38c phy: qcom-qmp-usb: Fix an NULL vs IS_ERR() bug
The qmp_usb_iomap() helper function currently returns the raw result of
devm_ioremap() for non-exclusive mappings. Since devm_ioremap() may return
a NULL pointer and the caller only checks error pointers with IS_ERR(),
NULL could bypass the check and lead to an invalid dereference.

Fix the issue by checking if devm_ioremap() returns NULL. When it does,
qmp_usb_iomap() now returns an error pointer via IOMEM_ERR_PTR(-ENOMEM),
ensuring safe and consistent error handling.

Signed-off-by: Chenyuan Yang <chenyuan0y@gmail.com>
Fixes: a5d6b1ac56 ("phy: qcom-qmp-usb: fix memleak on probe deferral")
CC: Johan Hovold <johan@kernel.org>
CC: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250414125050.2118619-1-chenyuan0y@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:29:44 +01:00
Siddharth Vadapalli
e00c9aea31 dt-bindings: phy: cadence-torrent: enable PHY_TYPE_USXGMII
The Cadence Torrent SERDES supports USXGMII protocol. Hence, update the
bindings to allow PHY_TYPE_USXGMII. Since PHY_TYPE_USXGMII has the value
of "12" while the existing maximum allowed PHY TYPE is "9", switch back to
using "enum" property in the bindings to account for this discontinuity.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250411055743.623135-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:26:05 +01:00
Richard Leitner
6a09ae8281 leds: flash: Add support for flash/strobe duration
Add support for the new V4L2_CID_FLASH_DURATION control to the LEDs
driver.

Signed-off-by: Richard Leitner <richard.leitner@linux.dev>
Link: https://lore.kernel.org/r/20250507-ov9282-flash-strobe-v4-2-72b299c1b7c9@linux.dev
Signed-off-by: Lee Jones <lee@kernel.org>
2025-05-14 09:25:09 +01:00
Christophe JAILLET
f1c86ab986 leds: rgb: leds-mt6370-rgb: Improve definition of some struct linear_range
Use LINEAR_RANGE() instead of hand-writing it. It is more robust, should
the layout of the structure change one day.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/1ce4245107e0a51dce502a007a69899bda018d5f.1746197460.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Lee Jones <lee@kernel.org>
2025-05-14 09:25:08 +01:00
Lee Jones
cfa40f29df leds: led-test: Provide tests for the lookup and get infrastructure
This API allows providers to offer an specific LED to be looked-up by a
consumer.  Consumers are then able to describe the aforementioned LED
and take a reference on it.

For convenience, we're testing both sides of the API in just one test
function here.  In reality, both the provider and the consumer would be
logistically orthogonal.

CMD:
  tools/testing/kunit/kunit.py run --kunitconfig drivers/leds

RESULTS:
  [16:38:57] Configuring KUnit Kernel ...
  [16:38:57] Building KUnit Kernel ...
  Populating config with:
  $ make ARCH=um O=.kunit olddefconfig
  Building with:
  $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=20
  [16:39:02] Starting KUnit Kernel (1/1)...
  [16:39:02] ============================================================
  Running tests with:
  $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
  [16:39:03] ===================== led (2 subtests) =====================
  [16:39:03] [PASSED] led_test_class_register
  [16:39:03] [PASSED] led_test_class_add_lookup_and_get
  [16:39:03] ======================= [PASSED] led =======================
  [16:39:03] ============================================================
  [16:39:03] Testing complete. Ran 2 tests: passed: 2
  [16:39:03] Elapsed time: 6.255s total, 0.001s configuring, 5.131s building, 1.106s running

Link: https://lore.kernel.org/r/20250501081918.3621432-3-lee@kernel.org
Signed-off-by: Lee Jones <lee@kernel.org>
2025-05-14 09:25:07 +01:00
Lee Jones
eb58933b78 leds: led-test: Fill out the registration test to cover more test cases
Upon successful LED class device registration, it is expected that
certain attributes are filled out in pre-defined ways.  For instance, if
provided, the .brightness_get() call-back should be called to populate
the class device 'brightness' attribute, 'max_brightness' should be
initialised as LED_FULL (at least until we can rid these pesky enums)
and the sysfs group should be created with the class device name
supplied by the caller.

If subsequent registrations take place that would result in name
conflicts, various outcomes are expected depending on which flags are
set.  If LED_REJECT_NAME_CONFLICT is disabled, registration should
succeed resulting in an iteration on the provided name.  Conversely, if
it's enabled, then registration is expected to fail outright.

We test for all of these scenarios here.

Link: https://lore.kernel.org/r/20250501081918.3621432-2-lee@kernel.org
Signed-off-by: Lee Jones <lee@kernel.org>
2025-05-14 09:25:06 +01:00