Various fixes for the PS3 repository code:
- Sync signatures of function prototypes and implementations (enum vs.
unsigned int)
- Correct references to `regions' as `registers':
o Correct enum ps3_region_type as enum ps3_reg_type,
o Correct PS3_REGION_TYPE_* as PS3_REG_TYPE_*,
o Correct ps3_repository_find_region() as ps3_repository_find_reg().
- Correct function name in pr_debug() call
- Minor error condition improvements.
Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
It appears that EEH is improperly enabled for some Power4 systems.
On these systems, the ibm,set-eeh-option returns a value of success
even when EEH is not supported on the given node. Thus, an explicit
check for support is required.
During boot, on power4, without this patch, one sees messages
similar to:
EEH: event on unsupported device, rc=0 dn=/pci@400000000110/IBM,sp@1
EEH: event on unsupported device, rc=0 dn=/pci@400000000110/pci@2
EEH: event on unsupported device, rc=0 dn=/pci@400000000110/pci@2,2
etc.
The patch makes these go away.
Without this patch, EEH recovery does seem to work correctly for
at least some devices (I tested ethernet e1000), but fails to
recover others (the Emulex LightPulse LPFC, most notably).
Off the top of my head, I don't remember why some devices are
affected, but not others.
The PAPR indicates that the correct way to test for EEH is as
done in this patch; its not clear to me if this was in the PAPR
all along, or recently added; if it was there all along, its not
clear to me why this hadn't been fixed long ago. I suspect only
certain firmware levels are affected.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Replace an apparent typo of CONFIG_SERIAL_CPM_SMC with
CONFIG_SERIAL_CPM_SMC2.
Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This workaround was copy-pasted from the powermac code. It's not
necessary for maple.
Signed-off-by: Nathan Lynch <ntl@pobox.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This add support of the Freescale mpc86xads reference board to
arch/powerpc. Supported SMC1 and SMC2 (UART and serial console), FEC
100Mbps Ethernet, SCC1 Ethernet (10Mbps hdx)
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This adds the core 8xx stuff and specifically mpc885ads board-specific
bits to arch/powerpc. Respective Kconfig has been cleaned up from the stuff
not yet ported over to avoid confusion. Updated and cleaned version.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This covers common CPM access functions, CPM interrupt controller code,
micropatch and a few compatibility things to kee the same driver base
working with arch/ppc. This version is refined with all the comments
(mostly PIC-related) addressed.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Added 8xx SoC peripherials: fec for Ethernet and smc for UARTs.
Ordinary routines to extract values from the device tree and insert
respective platform devices
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Including support for non-coherent cache, some mm-related things +
relevant field in Kconfig and Makefiles. Also included rheap.o compilation
if 8xx is defined.
Non-coherent mapping were refined and renamed according to Cristoph
Hellwig. Orphaned functions were cleaned up.
[Also removed arch/ppc/kernel/dma-mapping.c, because otherwise
compiling with ARCH=ppc for a non DMA-cache-coherent platform ends up
with two copies of __dma_alloc_coherent etc.
-- paulus.]
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: (27 commits)
[IA64] swiotlb abstraction (e.g. for Xen)
[IA64] swiotlb cleanup
[IA64] make swiotlb use bus_to_virt/virt_to_bus
[IA64] swiotlb bug fixes
[IA64] Hook up getcpu system call for IA64
[IA64] clean up sparsemem memory_present call
[IA64] show_mem() for IA64 sparsemem NUMA
[IA64] missing exports hwsw_sync_...
[IA64] virt_to_page() can be called with NULL arg
[IA64] alignment bug in ldscript
[IA64] register memory ranges in a consistent manner
[IA64] Enable SWIOTLB only when needed
[IA64-SGI] Check for TIO errors on shub2 Altix
[IA64] remove bogus prototype ia64_esi_init()
[IA64] Clear IRQ affinity when unregistered
[IA64] fix ACPI Kconfig issues
[IA64] Fix NULL-pointer dereference in ia64_machine_kexec()
[IA64] find thread for user rbs address
[IA64] use snprintf() on features field of /proc/cpuinfo
[IA64] enable singlestep on system call
...
This is just a straight port of the same done in arch/ppc
by Marcelo Tosatti. One used to be
[PATCH] ppc32 8xx: update_mmu_cache() needs unconditional tlbie,
commit eb07d964b4
In a nutshell, the board is nearly stuck without this, yet without any
visible failure - being just very slow.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Instead of pinning per-cpu TLB into a DTR, use DTC. This will free up
one TLB entry for application, or even kernel if access pattern to
per-cpu data area has high temporal locality.
Since per-cpu is mapped at the top of region 7 address, we just need to
add special case in alt_dtlb_miss. The physical address of per-cpu data
is already conveniently stored in IA64_KR(PER_CPU_DATA). Latency for
alt_dtlb_miss is not affected as we can hide all the latency. It was
measured that alt_dtlb_miss handler has 23 cycles latency before and
after the patch.
The performance effect is massive for applications that put lots of tlb
pressure on CPU. Workload environment like database online transaction
processing or application uses tera-byte of memory would benefit the most.
Measurement with industry standard database benchmark shown an upward
of 1.6% gain. While smaller workloads like cpu, java also showing small
improvement.
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
It's not efficient to use a per-cpu variable just to store
how many physical stack register a cpu has. Ever since the
incarnation of ia64 up till upcoming Montecito processor, that
variable has "glued" to 96. Having a variable in memory means
that the kernel is burning an extra cacheline access on every
syscall and kernel exit path. Such "static" value is better
served with the instruction patching utility exists today.
Convert ia64_phys_stacked_size_p8 into dynamic insn patching.
This also has a pleasant side effect of eliminating access to
per-cpu area while psr.ic=0 in the kernel exit path. (fixable
for per-cpu DTC work, but why bother?)
There are some concerns with the default value that the instruc-
tion encoded in the kernel image. It shouldn't be concerned.
The reasons are:
(1) cpu_init() is called at CPU initialization. In there, we
find out physical stack register size from PAL and patch
two instructions in kernel exit code. The code in question
can not be executed before the patching is done.
(2) current implementation stores zero in ia64_phys_stacked_size_p8,
and that's what the current kernel exit path loads the value with.
With the new code, it is equivalent that we store reg size 96
in ia64_phys_stacked_size_p8, thus creating a better safety net.
Given (1) above can never fail, having (2) is just a bonus.
All in all, this patch allow one less memory reference in the kernel
exit path, thus reducing syscall and interrupt return latency; and
avoid polluting potential useful data in the CPU cache.
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
arch/mips/lib/uncached.c: In function 'run_uncached':
arch/mips/lib/uncached.c:47: warning: comparison is always true due to limited range of data type
arch/mips/lib/uncached.c:48: warning: comparison is always false due to limited range of data type
arch/mips/lib/uncached.c:57: warning: comparison is always true due to limited range of data type
arch/mips/lib/uncached.c:58: warning: comparison is always false due to limited range of data type
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The N32 and O32 pselect6 syscalls need to use compat_sys_pselect6 to
translate arguments from 32-bit to 64-bit layout.
Signed-off-by: Joseph Myers <joseph@codesourcery.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch adds LSM hooks into the setaffinity and getaffinity functions
for the mips architecture to enable security modules to control these
operations between tasks with different security attributes. This
implementation uses the existing task_setscheduler and task_getscheduler
LSM hooks.
Signed-Off-By: David Quigley <dpquigl@tycho.nsa.gov>
Acked-by: Stephen Smalley <sds@tycho.nsa.gov>
Signed-off-by: James Morris <jmorris@namei.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
CC arch/mips/au1000/pb1100/board_setup.o
arch/mips/au1000/pb1100/board_setup.c: In function ‘board_setup’:
arch/mips/au1000/pb1100/board_setup.c:104: warning: passing argument 1 of ‘readb’ makes pointer from integer without a cast
arch/mips/au1000/pb1100/board_setup.c:105: warning: passing argument 1 of ‘readb’ makes pointer from integer without a cast
arch/mips/au1000/pb1100/board_setup.c:105: warning: passing argument 2 of ‘writeb’ makes pointer from integer without a cast
arch/mips/au1000/pb1100/board_setup.c:109: warning: passing argument 1 of ‘readb’ makes pointer from integer without a cast
arch/mips/au1000/pb1100/board_setup.c:110: warning: passing argument 1 of ‘readb’ makes pointer from integer without a cast
arch/mips/au1000/pb1100/board_setup.c:110: warning: passing argument 2 of ‘writeb’ makes pointer from integer without a cast
arch/mips/au1000/pb1100/board_setup.c:51: warning: unused variable ‘sys_clksrc’
arch/mips/au1000/pb1100/board_setup.c:51: warning: unused variable ‘sys_freqctrl’
arch/mips/au1000/pb1100/board_setup.c:50: warning: unused variable ‘pin_func’
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
CC arch/mips/au1000/common/pci.o
arch/mips/au1000/common/pci.c:42: warning: large integer implicitly truncated to unsigned type
arch/mips/au1000/common/pci.c:43: warning: large integer implicitly truncated to unsigned type
arch/mips/au1000/common/pci.c:49: warning: large integer implicitly truncated to unsigned type
arch/mips/au1000/common/pci.c:50: warning: large integer implicitly truncated to unsigned type
arch/mips/au1000/common/pci.c: In function ‘au1x_pci_setup’:
arch/mips/au1000/common/pci.c:82: warning: ISO C90 forbids mixed declarations and code
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
early_serial_setup is only defined when CONFIG_SERIAL_8250 is set.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
pb1200/irqmap.c had been broken a while due to non-named initializer
and had missed some recent IRQ related changes. Apply these commits
to this file.
[MIPS] IRQ cleanups
commit 1603b5aca4
[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq
commit 1417836e81
[MIPS] Compile __do_IRQ() when really needed
commit e77c232cfc
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Given that the Makefiles involved already have conditional compilation of
the form:
obj-$(CONFIG_KGDB) += dbg_io.o
there seems to be little value for the dbg_io.c source files to check
that config variable yet again.
Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This get rid of some undesirable hole in BSS section due to random
order of placement.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The "typename" field was obsoleted by the "name" field.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Currently KEXEC is in "Machine selection", SECCOMP, PM, APM are in
"Executable file formats" menu. Move KEXEC and SECCOMP to "Kernel
type" and PM, APM to new "Power management options" menu. Also
replace "config PM" with kernel/power/Kconfig.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch has added MACINT controls.
They are necessary for VR4133 ethernet driver.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The old code was assuming that min_low_pfn was always 0. This
means that platforms having a big hole at their memory start
paid the price of wasting some memory for the allocation of
unused entries in mem_map[].
This patch prevents this waste.
It introduces PHYS_OFFSET define which is the start of the
physical memory and uses it wherever needed. Specially when
converting physical/virtual addresses into virtual/physical
ones.
Currently all platforms defines PHYS_OFFSET to 0.
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch makes a better usage of these two globals.
'min_low_pfn' is now correctly setup for all configs, which
allow us to rely on it in boot memory code init.
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The 32-bit version and 64-bit version are almost equal. Unify them.
This makes further improvements (for example, supporting CDEX, etc.)
easier.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Current prom_free_prom_memory() implementations are almost same as
free_init_pages(), or no-op. Make free_init_pages() extern (again)
and make prom_free_prom_memory() use it.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
