Add Ether clock and platform device for R8A7778 SoC; add a function to register
this device with board-specific platform data.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Ether clock and platform device for R8A7779 SoC; add a function to register
this device with board-specific platform data.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
We want a strends() function next, so make one and use it appropriately,
making new_module() arg const while we're at it.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Daniel writes:
Highlights:
- Imre's for_each_sg_pages rework (now also with the stolen mem backed
case fixed with a hack) plus the drm prime sg list coalescing patch from
Rahul Sharma. I have some follow-up cleanups pending, already acked by
Andrew Morton.
- Some prep-work for the crazy no-pch/display-less platform by Ben.
- Some vlv patches, by far not all (Jesse et al).
- Clean up the HDMI/SDVO #define confusion (Paulo)
- gen2-4 vblank fixes from Ville.
- Unclaimed register warning fixes for hsw (Paulo). More still to come ...
- Complete pageflips which have been stuck in a gpu hang, should prevent
stuck gl compositors (Ville).
- pm patches for vt-switchless resume (Jesse). Note that the i915 enabling
is not (yet) included, that took a bit longer to settle. PM patches are
acked by Rafael Wysocki.
- Minor fixlets all over from various people.
* tag 'drm-intel-next-2013-03-23' of git://people.freedesktop.org/~danvet/drm-intel: (79 commits)
drm/i915: Implement WaSwitchSolVfFArbitrationPriority
drm/i915: Set the VIC in AVI infoframe for SDVO
drm/i915: Kill a strange comment about DPMS functions
drm/i915: Correct sandybrige overclocking
drm/i915: Introduce GEN7_FEATURES for device info
drm/i915: Move num_pipes to intel info
drm/i915: fixup pd vs pt confusion in gen6 ppgtt code
style nit: Align function parameter continuation properly.
drm/i915: VLV doesn't have HDMI on port C
drm/i915: DSPFW and BLC regs are in the display offset range
drm/i915: set conservative clock gating values on VLV v2
drm/i915: fix WaDisablePSDDualDispatchEnable on VLV v2
drm/i915: add more VLV IDs
drm/i915: use VLV DIP routines on VLV v2
drm/i915: add media well to VLV force wake routines v2
drm/i915: don't use plane pipe select on VLV
drm: modify pages_to_sg prime helper to create optimized SG table
drm/i915: use for_each_sg_page for setting up the gtt ptes
drm/i915: create compact dma scatter lists for gem objects
drm/i915: handle walking compact dma scatter lists
...
Make sure media_entity_pipeline_stop() is called on video device
close in cases where there was VIDIOC_STREAMON ioctl and no
VIDIOC_STREAMOFF. This patch fixes media entities stream_count
state which could prevent links from being disconnected, due to
non-zero stream_count.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This patch fixes erroneous setup of the YUV order caused by not
clearing FIMC_REG_MSCTRL_ORDER422_MASK bit field before setting
proper FIMC_REG_MSCTRL_ORDER422 bits. This resulted in false
colors for YUYV, YVYU, UYVY, VYUY color formats, depending in
what sequence those were configured by user space.
YUV order definitions are corrected so that following convention
is used:
| byte3 | byte2 | byte1 | byte0
-------+-------+-------+-------+------
YCBYCR | CR | Y | CB | Y
YCRYCB | CB | Y | CR | Y
CBYCRY | Y | CR | Y | CB
CRYCBY | Y | CB | Y | CR
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
The FIMC-LITE output DMA allows to configure different YUV order
than the order at the camera input interface. Thus there is some
limited colorspace conversion possible. This patch makes the
color format variable be per FIMC-LITE input/output, rather than
a global per device. This also fixes incorrect behavior where
color format at the FIMC-LITE.N subdev's source pad is modified
by VIDIOC_S_FMT ioctl on the related video node.
YUV order definitions are corrected so that we use notation:
| byte3 | byte2 | byte1 | byte0
-------+-------+-------+-------+------
YCBYCR | CR | Y | CB | Y
YCRYCB | CB | Y | CR | Y
CBYCRY | Y | CR | Y | CB
CRYCBY | Y | CB | Y | CR
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
There is no need to use separate variant data structure for each
FIMC-LITE IP instance. According to my knowledge there are no
differences across them on Exynos4 as well as Exynos5 SoCs. Drop
flite_variant data structure and use struct flite_drvdata instead.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
The Exynos platform will support only device tree based booting
from v3.10. The FIMC variant data will be parsed directly from
the device tree, hence the now unused static data can be removed.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Create disabled links from the FIMC-LITE subdevs to the FIMC-IS-ISP
subdev and from FIMC-IS-ISP to all FIMC subdevs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Adding the PM configuration of PMC when the platform support suspend
function.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds "non-removable" property of MMC host where the eMMC device
is for Tegra platform.
And the "keep-power-in-suspend" property was used for the SDIO device that
need this to go into suspend mode (e.g. BRCM43xx series).
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This adds the power gpio key to DT and enable the wakeup of the gpio key
for the device. The Seaboard and paz00 already had the power gpio key
binding and the power key of Whistler was on KBC. So these boards' device
tree didn't include in this patch.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Set "regulator-always-on" for the SD slot on Dalmore, so that SD cards
work. This used to work, since this regulator is on by default, but was
broken by commit "ARM: tegra: dalmore: add TPS65090 node", since that
didn't specify always-on for this regulator.
In the long run, the regulators should all be hooked up to the SDHCI
device nodes. However, we haven't done that for any of the Tegra boards
yet, so to be consistent, this patch simply forces the regulator on,
rather than hooking it up and making it work differently to other boards.
Reported-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 reference platform Dalmore has voltage switch
regulators which are controlled by the Tegra GPIOs.
Add DT node for fixed regulators.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 reference platform, Dalmore, uses the TPS65090 as
secondary PMICs which is mainly act as voltage switch regulator
controlled by i2c communication.
Add DT node for TPS65090.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: remove unit-address from node name since it's unique already]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Dalmore uses the TPS51632 as CPU regulator. The device is connected
on I2C5.
Add DT node for TPS51632.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds the node for the bq20z45 I2C gas gauge which is
compatible with the sbs-battery power supply driver.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[swarren: remove unit-address from node name since it's unique already]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add documentation for device tree binding of NVIDIA's Tegra I2C
controller driver.
Describing all compatible values used for different Tegra SoCs
in details in this documentation.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed a couple typos, trimmed examples]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 has 6 SPI controllers. These controllers are
redesign on T114 with different register interface.
Add DT entry for spi controllers and make it compatible with
"nvidia,tegra114-spi", since they are a new incompatible design.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed reg property for 3rd SPI controller]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
supports 11x8 type of matrix. The number of rows and columns
are configurable.
Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc".
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add APB DMA requestor and serial aliases for serial controller.
There are two serial drivers i.e. 8250 based simple serial driver
and APB DMA based serial driver for higher baudrate and performace.
The simple serial driver is selected by compatible value
"nvidia,tegra114-uart", "nvidia,tegra20-uart", and the APB DMA based
driver is selected by compatible value "nvidia,tegra114-hsuart",
"nvidia,tegra30-hsuart".
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 has 5 I2C controllers. These controllers have the
following changes which makes incompatible with previous hardware:
- Single clock source to I2C controller.
- Interrupt support for per packet transfer.
Add DT entry for I2C controllers and make it compatible with
"nvidia,tegra114-i2c".
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed location of status property for consistency]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".
Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA
controller driver as in Tegra114, the global pause also clock gate the
DMA register and hence it iw not possible to write the DMA register
with global pause.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed DT node order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds a device tree node for the four PWM controllers present
on Tegra114.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
We should be defining the PWM nodes with status as "disabled" in the
chip-specific dtsi file, since we don't know whether specific boards
will use the PWM or not. This patch fixes the PWM node status for
Tegra20 and Tegra30.
Also fixed the one user of PWM, which is the Tegra20 medcom-wide board,
so that PWM is set to "okay" in the board-specific dts file.
Signed-off-by: Andrew Chew <achew@nvidia.com>
[swarren: in medcom-wide: fixed node sort order, removed duplicate pwm:
label, fixed syntax error]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Dalmore has a built-in eMMC device and a user-accessible SD card slot.
Add device tree nodes to enable these.
Based on changes by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[swarren: added commit description, fixed DT node sort order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds in the SDHCI nodes for the busses supported on Tegra114
boards.
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
[Rhyland added clk refs to & reordered sdhci nodes and removed spaces]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[swarren: fixed DT node sort order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The USB PHY nodes are all grouped together rather than being sorted based
on reg address like all other nodes fix this.
I apologize for the churn; I should have noticed this during review of the
patches that caused this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds support for registration of the FIMC-IS device
represented by the FIMC-IS-ISP subdev to the top level media device
driver. The FIMC-IS subsystem is available on Exynos4x12 SoCs which
support only device tree based booting.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
A gap exists in the binding's clock ID definitions. Fix the clock driver
to be consistent. This allows pclk to be looked up through device tree
and prevents:
ERROR: could not get clock /pmc:pclk(0)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The UART driver enables the console uart clock, so we don't need to do that
anymore in this file.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Implement clocks for Tegra114.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds DT binding documentaton for the Imaging Subsystem
(camera ISP) found on Samsung Exynos4x12 SoCs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This patch adds a common image sensor driver and Makefile/Kconfig
to enable compilation of the whole IS driver.
The sensor subdev driver currently only handles an image sensor's
power supplies and reset signal. There is no I2C communication as
it is handled by the ISP's firmware.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This patch adds the ISP I2C bus controller driver files.
Creating a standard I2C bus adapter, even if the driver doesn't
actually communicate with the hardware and it is instead
controlled by the ISP firmware running on the Cortex-A5, allows
to use standard hardware description in the device tree. As the
sensor would have actually had a standard V4L2 sub-device driver
run on the host CPU.
This approach allows to adapt the driver with a relatively small
effort should the Imaging Subsystem architecture change so that
the I2C bus is handled by the host's CPU OS, rather than the
internal FIMC-IS ARM CPU firmware. The image sensor driver could
be a standard I2C client driver, as in case of most existing
image sensors.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This patch adds a set of core files of the Exynos4x12 FIMC-IS
V4L2 driver. This includes main functionality like allocating
memory, loading the firmware, FIMC-IS register interface and
host CPU <-> IS command and error code definitions.
The driver currently exposes a single subdev named FIMC-IS-ISP,
which corresponds to the FIMC-IS ISP and DRC IP blocks.
The FIMC-IS-ISP subdev currently supports only a subset of user
controls. For other controls we need several extensions at the
V4L2 API. The supported standard controls are:
brightness, contrast, saturation, hue, sharpness, 3a_lock,
exposure_time_absolute, white_balance_auto_preset,
iso_sensitivity, iso_sensitivity_auto, exposure_metering_mode.
Signed-off-by: Younghwan Joo <yhwan.joo@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
