We should not always presume all kernels use pfifo_fast as the default qdisc.
For example, a fq_codel qdisk could have below output:
qdisc fq_codel 0: parent 1:4 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64
Reported-by: kernel test robot <lkp@intel.com>
Suggested-by: Peilin Ye <peilin.ye@bytedance.com>
Signed-off-by: Li Zhijian <zhijianx.li@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
qca8k has a global MTU, so its tracking the MTU per port to make sure
that the largest MTU gets applied.
Since it uses the frame size instead of MTU the driver MTU change function
will then add the size of Ethernet header and checksum on top of MTU.
The driver currently populates the per port MTU size as Ethernet frame
length + checksum which equals 1518.
The issue is that then MTU change function will go through all of the
ports, find the largest MTU and apply the Ethernet header + checksum on
top of it again, so for a desired MTU of 1500 you will end up with 1536.
This is obviously incorrect, so to correct it populate the per port struct
MTU with just the MTU and not include the Ethernet header + checksum size
as those will be added by the MTU change function.
Fixes: f58d2598cf ("net: dsa: qca8k: implement the port MTU callbacks")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
With SGMII phy the internal delay is always applied to the PAD0 config.
This is caused by the falling edge configuration that hardcode the reg
to PAD0 (as the falling edge bits are present only in PAD0 reg)
Move the delay configuration before the reg overwrite to correctly apply
the delay.
Fixes: cef0811584 ("net: dsa: qca8k: set internal delay also for sgmii")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Guangbin Huang says:
====================
ethtool: add support to set/get tx copybreak buf size and rx buf len
This series add support to set/get tx copybreak buf size and rx buf len via
ethtool and hns3 driver implements them.
Tx copybreak buf size is used for tx copybreak feature which for small size
packet or frag. Use ethtool --get-tunable command to get it, and ethtool
--set-tunable command to set it, examples are as follow:
1. set tx spare buf size to 102400:
$ ethtool --set-tunable eth1 tx-buf-size 102400
2. get tx spare buf size:
$ ethtool --get-tunable eth1 tx-buf-size
tx-buf-size: 102400
Rx buf len is buffer length of each rx BD. Use ethtool -g command to get
it, and ethtool -G command to set it, examples are as follow:
1. set rx buf len to 4096
$ ethtool -G eth1 rx-buf-len 4096
2. get rx buf len
$ ethtool -g eth1
...
RX Buf Len: 4096
Change log:
V5 -> V6
1.Fix compile error for divers/s390.
V4 -> V5
1.Change struct ethtool_ringparam_ext to kernel_ethtool_ringparam.
2.change "__u32 rx_buf_len" to "u32 rx_buf_len".
V3 -> V4
1.Fix a few allmodconfig compile warning.
2.Add more '=' synbol to ethtool-netlink.rst to refine format.
3.Move definement of struct ethtool_ringparam_ext to include/linux/ethtool.h.
4.Move related modify of rings_fill_reply() from patch 4/6 to patch 3/6.
V2 -> V3
1.Remove documentation for tx copybreak buf size, there is description for
it in userspace ethtool.
2.Move extending parameters for get/set_ringparam function from patch3/6
to patch 4/6.
V1 -> V2
1.Add documentation for rx buf len and tx copybreak buf size.
2.Extend structure ringparam_ext for extenal ring params.
3.Change type of ETHTOOL_A_RINGS_RX_BUF_LEN from NLA_U32 to
NLA_POLICY_MIN(NLA_U32, 1).
4.Add supported_ring_params in ethtool_ops to indicate if support external
params.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
The way to set tx spare buf via module parameter is not such
convenient as the way to set it via ethtool.
So,remove the way to set tx spare buf via module parameter.
Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Rx buf len is for rx BD buffer size, support setting it via ethtool -G
parameter and getting it via ethtool -g parameter.
Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add two new parameters kernel_ringparam and extack for
.get_ringparam and .set_ringparam to extend more ring params
through netlink.
Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add support to set rx buf len via ethtool -G parameter and get
rx buf len via ethtool -g parameter.
Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Tx copybreak buf size is used for tx copybreak feature, the feature is
used for small size packet or frag. It adds a queue based tx shared
bounce buffer to memcpy the small packet when the len of xmitted skb is
below tx_copybreak(value to distinguish small size and normal size),
and reduce the overhead of dma map and unmap when IOMMU is on.
Support setting it via ethtool --set-tunable parameter and getting
it via ethtool --get-tunable parameter.
Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add support for ethtool to set/get tx copybreak buf size.
Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
With VT-d disabled on Intel platform, ath11k gets only one MSI
vector. In that case, ath11k does not free IRQ when doing suspend,
hence the kernel has to migrate it to CPU0 (if it was affine to
other CPUs) and allocates a new MSI vector. However, ath11k has
no chance to reconfig it to HW srngs during this phase, thus
ath11k fails to resume.
This issue can be fixed by setting IRQ affinity to CPU0 before
request_irq is called. With such affinity, migration will not
happen and thus the vector keeps unchanged during suspend/resume.
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1
Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20211026041732.5323-1-bqiang@codeaurora.org
Current code enables ASPM by default, it allows MHI to enter M2 state.
In case of one MSI vector, system hang is observed if ath11k does MHI
register reading in this state. The issue was reported on Dell XPS 13
9310 but is seen also on XPS 15 and XPS 17 laptops.
The workaround here is to prevent MHI from entering M2 state, this can
be done by disabling ASPM if only one MSI vector is used. When using 32
vectors ASPM is enabled as before.
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1
Signed-off-by: Carl Huang <cjhuang@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Link: https://lore.kernel.org/r/20211026041722.5271-1-bqiang@codeaurora.org
On some platforms it's not possible to allocate 32 MSI vectors for various
reasons, be it kernel configuration, VT-d disabled, buggy BIOS etc. So
ath11k was not able to use QCA6390 PCI devices on those platforms. Add
support for one MSI vector to solve that.
In case of one MSI vector, interrupt migration needs to be disabled. This
is because when interrupt migration happens, the msi_data may change.
However, msi_data is already programmed to rings during initial phase and
ath11k has no way to know that msi_data is changed during run time and
reprogram again.
In case of one MSI vector, MHI subsystem should not use IRQF_NO_SUSPEND
as QCA6390 doesn't set this flag too. Ath11k doesn't need to leave
IRQ enabled in suspend state.
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1
Signed-off-by: Carl Huang <cjhuang@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Link: https://lore.kernel.org/r/20211026041714.5219-1-bqiang@codeaurora.org
This is to prepare for one MSI vector support. IRQ enable and disable
of CE and DP are done only in case of multiple MSI vectors.
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1
Signed-off-by: Carl Huang <cjhuang@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Link: https://lore.kernel.org/r/20211026041705.5167-1-bqiang@codeaurora.org
Like ATH11K_PCI_IRQ_CE0_OFFSET, define ATH11K_PCI_IRQ_DP_OFFSET for
DP to save the IRQ instead of base_vector from MSI config.
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1
Signed-off-by: Carl Huang <cjhuang@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Link: https://lore.kernel.org/r/20211026041655.5112-1-bqiang@codeaurora.org
This change adds two flags to indicate whether IRQ handler for CE
and DP can be called. This is because in one MSI vector case,
interrupt is not disabled in hif_stop and hif_irq_disable. Otherwise,
MHI interrupt is disabled too.
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1
Signed-off-by: Carl Huang <cjhuang@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Link: https://lore.kernel.org/r/20211026041646.5060-1-bqiang@codeaurora.org
The reservation mode of interrupts in kernel assigns a dummy vector
when the interrupt is allocated and assigns a real vector when the
request_irq is called. The reservation mode helps to ease vector
pressure when devices with a large amount of queues/interrupts
are initialized, but only a minimal subset of those queues/interrupts
is actually used.
So on reservation mode, the msi_data may change after request_irq
is called, so ath11k reads msi_data again after request_irq is called,
and then the correct msi_data is programmed into QCA6390 hardware
components. Without this change, spurious interrupt occurs in case of
one MSI vector. When VT-d in BIOS is enabled and ath11k can get 32 MSI
vectors, ath11k always get the same msi_data before and after request_irq,
that's why this change is only required when one MSI vector is to be
supported.
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1
Signed-off-by: Carl Huang <cjhuang@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20211026041636.5008-1-bqiang@codeaurora.org
The ARCH_FEATURES function ID is a 32-bit SMC call, which returns
a 32-bit result per the SMCCC spec. Current code is doing a 64-bit
comparison against -1 (SMCCC_RET_NOT_SUPPORTED) to detect that the
feature is unimplemented. That check doesn't work in a Hyper-V VM,
where the upper 32-bits are zero as allowed by the spec.
Cast the result as an 'int' so the comparison works. The change also
makes the code consistent with other similar checks in this file.
Fixes: 821b67fa46 ("firmware: smccc: Add ARCH_SOC_ID support")
Signed-off-by: Michael Kelley <mikelley@microsoft.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Couple of fixes for sparse warnings(type error assignment in voltage and
sensor protocols), add proper propagation of error from scmi_pm_domain_probe
handling agent discovery response in base protocol correctly and a fix
to avoid null pointer de-reference in the error path.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmGWO9sACgkQAEG6vDF+
4phNHQ//ZC41jfgB/oZkkUX7WUJov6nn9JPXOV8EB5sCUOVZfWF/dsamsuqK16x6
DZd9T5XU3M7c+Vn+s9PNzokpOaqAE2egfj1gV398skqeUZL/69nywRZCG27j4JBz
Jqbibdhz5yLTARhiK2NwMdGJiQYTV3X4rEl40ULzvhErWCuK1nNxr1rgU8uP0b/L
X4NEXqln1Jqt7vx7rGylDdUqZIqzTBqWZudNDrkW8eua2AwXSnvnLxrXEBvTv5Tp
hloBly9JA1vE/1tDPXxiNIR6IJwWn+zYqfKsxryyk7q9Ff8051Xv5H8dRVTwlPn8
nmwyBU/hsVRo6KGJaF8JgVaPFDWoXr39YpathL/qyNEQnTVjvfa7haVuf/2RTE1r
45bWZ5Qez40GihIGg9GWaLx3yta+X0lA0tTQ0vwpAe3enh6bH3+kIio4VlXr+3lu
SLFRkkzcSB+oi5bYySQwK+z2IIFY1FsUcIY0qfuEnuiPvNGkimSS086WMn5mTqvm
ak6idCXpxmHKlyMuswN+wueZSbvBaWjqSwbcSUB6omOZWuehkXASi5OGpVrpxNRW
TITQ8vVZv7ptysMEMKklrbY+HvNudVPeOqiGW1WmXzFtFZfBsBGfCL7DcjwEmC+J
QAu0u4BMC66t2FbEcKRbeOFmDGogqGbfsl9ZyRgts7ihOcCczTo=
=H/Sw
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmGbc0gACgkQmmx57+YA
GNmkDRAAtogx/+ch5neE1VFKOgFuW6AoASuwhMyXZjJyf4HbQyioPtiIJNMXeLb6
KuLMdCPiLJCquGaGS0dyyaQAc8OWXBMDNj5SvbQcu/HX63sSiaJL3iyZ9Inmkihm
z4p4lY8g07I8INdgw3pz4brBCsJTEdq20VTZnkxlACgaFlzZLEziIJw7D8XMv3/V
5PQEiLthIjt2IwtW0cD034H+T3ouHYQR9mZWoE3K4UeDGErgm/k6CcSm9jsmb4oh
uL5ufCv0Q0oKJBet/t3BjMGXUu43ysnCSRkYqFQR6EUjo3U2Y6/NPMMJyBrPS0h7
VqSHu00ri2JWoCgyF3cTCR3EXApHXILC18Va64jspPH4+8yVPcyL0VcJZus6eCkK
lBaps3gx7fhFfaw9pMVgdt23y0B5X8twDMpGRtyIWkxZyzbcjdgihxuSAPQtrFWm
rDRoXmUqsc73iW0MX9iQQy0idjbT1h28iPQmfaDtTZDf/rYJ9ywLRiUQGGZMfP1u
SYeXvMqmuwqZoQjsSU6TXkzUJiUS1Fdx3dc4AqMBLP08GgNgrFTraNrVik0HRVYq
bexP+svCyfGnvmz8JssT3hi1Xi5QHTmfN8v+tggIQomiBH8p2DCnDhIAh4RC4/TM
vWi+AsgFISJ30XDmvd3qL6bOVvPe18ZkC6VYIzNprRg9EoBLgqk=
=Q0ac
-----END PGP SIGNATURE-----
Merge tag 'scmi-fixes-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/fixes
Arm SCMI fixes for v5.16
Couple of fixes for sparse warnings(type error assignment in voltage and
sensor protocols), add proper propagation of error from scmi_pm_domain_probe
handling agent discovery response in base protocol correctly and a fix
to avoid null pointer de-reference in the error path.
* tag 'scmi-fixes-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scmi: Fix type error assignment in voltage protocol
firmware: arm_scmi: Fix type error in sensor protocol
firmware: arm_scmi: pm: Propagate return value to caller
firmware: arm_scmi: Fix base agent discover response
firmware: arm_scmi: Fix null de-reference on error path
Link: https://lore.kernel.org/r/20211118121656.4014764-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
5.16, please pull the following:
- Florian fixes the BCM5310x DTS include file to have the appropriate
I2C controller interrupt line, and allows the BCMA GPIO controller to
be used as an interrupt controller. Finally, the BCM2711 (Raspberry Pi
4) PCIe Device Tree node interrupts are fixed to list the correct
interrupt output as well as the INTB/C/D lines.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmGUD3AACgkQh9CWnEQH
BwSlDA/+IonkOHVzxFngOmahDm5kxmm5xwdTR3/x2GjdzRV0Mw93n1TaszYxFldu
QBpBp2BuMbZY9JSNxNWe43qc0PB09LEvL4zE+V8kO+DsuH8lCB3KIa0Wy5+PLV+5
6K7iqaI5yLxMl1ILb9xA0hULNiFOQmGOgXjAtSbnn5Av5vUclMwu2+PmXKM20lDn
QcjqE5luwpaZFiaNxhjGR4vnkoLGXtaR20Dd1bNW1/H7QQr6hicv7f0lXhoteXQA
dSctkKCRviSjdubVWaJhLLi6u2zQ3ADv7Y/ZRCdNFCSX3jl5ub9nBTe0XdE8aOYv
txySCAfp65DZatCTp1l5blR1Aav8qNvE13axVru/6rjdPNTHEttpIQJhBW1VeTBQ
vfWeP8sYYydZK7lw8TypF0OVolgDETlDs4ky/fEjcwyyCgfENwnVDxFFYuUub+NC
kUmawxe0j0ASOFje7BsORnwU0dHYUuob/3eiC5bdFIpSzMMXsypYB5c+uA3I0HQ0
Kjo6DbvkKmcW0FAmklWw27C9Uv6lcrzwDCLrUFEmdFjU5nPwFlgfLBMrZfGGQN1G
wLq9BYqt2Yy46bVwC1nYreGy3mJaYuPbGvqKjYaX48H572ZDP5JaHwpDCMCKHxlg
qKVXu+VhmNfnf7KBd7BOa2jsvOuovszRJfR+6EoCDXmUyoi60rM=
=Q2ZC
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmGbaggACgkQmmx57+YA
GNl2Cg//TK3ET0EJETxz2kBj+UwV4E0JxHapMkKtjUST+CHusnqP55cDr37BzPOx
eXga54gj1J3W0tvsyJ3DqDwwuRgWSbL2/6vuZxnkz6dmzm1I9HJ5+pZ6pUKbftUD
WEx+H/E8CBR0RTj63XViyFGhUWq+g0vvCrBR7Sh0LOQtXOzGXGwsvH91wKc+mHG4
onkuI0y592LsUoYsulacURHRV4GWu7raG7rKV3lo5MdKZ8Yf4CI1LDLzGT5LyYY/
7+3Mw8Zy8m/v49DscvPFB1bvyAxAspd5eBEKoJoOAG8U3pytG5zv+3RVR2tStJE2
DsBkhqKp9VaLURVo/haQP+gILXC3cWQv2hwadgA5m5qRLV011x/a3lLV74co9Mrp
BdjqVFsI8Xr2UmKDtsXrV74yOM7CjmfzHZV+TZiiRc8KEFK4ospni3Zjw1BaKa2i
+nOy7Q4BylSNrU+5/MLOYEPzlr2eFfUy98efZof6QOcTnCBICmy5aDOjVUt7J0Zm
9T9u78pGDy9pEkuM42cAjtbc97Iw5J6mAUbRo4IgqgLjp16zJT7bQUpScuYHlCQ6
1DBzPg2DtvA+cF2MaMboPROsXnifEVqdfnksf8h1tsr70hE9FIEaSZ2XjUuHaNg4
96exYOSvtRTfyqEeI6PI+YXwc42M5P/TTlTyd6LD6XvkXzbSjwA=
=jqJa
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.16/devicetree-fixes' of https://github.com/Broadcom/stblinux into arm/fixes
This pull request contains Broadcom ARM-based SoCs Device Tree fixes for
5.16, please pull the following:
- Florian fixes the BCM5310x DTS include file to have the appropriate
I2C controller interrupt line, and allows the BCMA GPIO controller to
be used as an interrupt controller. Finally, the BCM2711 (Raspberry Pi
4) PCIe Device Tree node interrupts are fixed to list the correct
interrupt output as well as the INTB/C/D lines.
* tag 'arm-soc/for-5.16/devicetree-fixes' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm2711: Fix PCIe interrupts
ARM: dts: BCM5301X: Add interrupt properties to GPIO node
ARM: dts: BCM5301X: Fix I2C controller interrupt
Link: https://lore.kernel.org/r/20211116201429.2692786-1-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Don't use _HIZ macros but also provide a val. This is more consistent
with the other macros and, thus, easier to read. Also shorter.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211119110442.4946-1-wsa+renesas@sang-engineering.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Instead of writing fixed values with undocumented bits which happen to
be set on some SoCs, better switch to read-modify-write operations
changing only bits which are documented. This is way more future-proof
as we don't know yet how these bits may be on upcoming SoCs.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211117093710.14430-1-wsa+renesas@sang-engineering.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
No need to open code regmap_update_bits().
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211117102902.20062-1-wsa+renesas@sang-engineering.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Some clocks shouldn't be automatically disabled in clk_disable_unused(),
otherwise kernel hangs. Mark those clocks with:
- CLK_IS_CRITICAL flag, when there won't be any consumers for that
clock, but system can't function when it's gated
- CLK_IGNORE_UNUSED flag, when consumer driver will be probably added
later
That makes it possible to run the kernel without passing the
"clk_ignore_unused" param.
Next clocks were modified:
- "gout_dpu_cmu_dpu_pclk": CLK_IGNORE_UNUSED
Will be enabled later in DSIM driver (Display Serial Interface
Master).
- "gout_gpio_peri_pclk": CLK_IGNORE_UNUSED
"gout_gpio_cmgp_pclk": CLK_IGNORE_UNUSED
"gout_gpio_hsi_pclk": CLK_IGNORE_UNUSED
Should be probably enabled in corresponding GPIO driver later, or
made CLK_IS_CRITICAL. "gout_gpio_peri_clk" is actually used by LEDs
on Exynos850-based dev board, so kernel hangs if this clock is not
running. Other clocks were marked as "ignore unused" to prevent
similar issues for other use cases or boards that might be added
later.
- "gout_cci_aclk": CLK_IS_CRITICAL
CCI (Cache Coherent Interconnect): obviously is critical.
- "gout_gic_clk": CLK_IS_CRITICAL
GIC (Generic Interrupt Controller): obviously is critical.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211121232741.6967-7-semen.protsenko@linaro.org
CMU_CMGP clock domain provides clocks for CMGP IP-core (Common GPIO).
CMGP module encapsulates next blocks:
- 8 GPIO lines
- 1 GPADC
- 2 USI blocks, each can be configured to provide one of
UART/SPI/HSI2C serial interfaces
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211121232741.6967-5-semen.protsenko@linaro.org
CMU_CMGP generates USI and ADC clocks for BLK_ALIVE. In particular USI
clocks are needed for HSI2C_3 and HSI2C_4 instances.
Add clock indices and bindings documentation for CMU_CMGP domain.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211121232741.6967-4-semen.protsenko@linaro.org
CMU_APM clock domain provides clocks for APM IP-core (Active Power
Management). According to Exynos850 TRM, CMU_APM generates I3C, Mailbox,
Speedy, Timer, WDT, RTC and PMU clocks for BLK_ALIVE.
This patch adds next clocks:
- bus clocks in CMU_TOP needed for CMU_APM
- all internal CMU_APM clocks
- leaf clocks for I3C, Speedy and RTC IP-cores
- bus clocks for CMU_CMGP and CMU_CHUB
CMU_APM doesn't belong to Power Domains, but platform driver is used for
its registration to keep its bus clock always running. Otherwise rtc-s3c
driver disables that clock and system freezes.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211121232741.6967-3-semen.protsenko@linaro.org
CMU_APM generates clocks for APM IP-core (Active Power Management). In
particular it generates RTC clocks, which are needed to enable rtc-s3c
driver on Exynos850 SoC.
Add clock indices and binding documentation for CMU_APM.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211121232741.6967-2-semen.protsenko@linaro.org
Some platforms, like the v3s, have DMA channels assigned to the crypto
engine, which were in the DTSI but were never documented.
Let's make sure they are.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20211116143255.385480-1-maxime@cerno.tech
Beelink X2 doesn't use HW CEC controller found in DW HDMI core. It has
dedicated GPIO pin for that purpose.
Add a node for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211120102024.439456-1-jernej.skrabec@gmail.com
Experimentation determined that HDMI CEC controller inside DW HDMI block
depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC
communication starts or stops working, depending on situation.
SoC user manual doesn't say anything about CEC, so this was overlooked.
Fix this by adding dependency to RTC 32k clock.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211120073448.32480-3-jernej.skrabec@gmail.com
Experimentation determined that HDMI CEC controller inside DW HDMI block
depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC
communication starts or stops working, depending on situation.
SoC user manual doesn't say anything about CEC, so this was overlooked.
Fix this by adding dependency to RTC 32k clock.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211120073448.32480-2-jernej.skrabec@gmail.com
Nodes are not sorted alphabetically. Do it.
There is no functional change.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211121070321.601659-1-jernej.skrabec@gmail.com
Tanix TX6 has a LED display driven by FD650.
Currently there is no Linux driver nor any binding for it. However, we
can at least provide I2C node in DT, so user space scripts or programs
can manually control it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211121115002.693329-1-jernej.skrabec@gmail.com
Function sunxi_rsb_hw_exit() is sometimes called with pm runtime
disabled, so in such cases pm_runtime_resume() will fail with -EACCES.
Instead of doing whole dance of enabling pm runtime and thus clock just
to disable it again immediately, just check if disabling clock is
needed. That way calling pm_runtime_resume() is not needed at all.
Fixes: 4a0dbc12e6 ("bus: sunxi-rsb: Implement runtime power management")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211121083537.612473-1-jernej.skrabec@gmail.com
While it is useful to build all of the CCU drivers at once, only 1-3 of
them will be loaded at a time, or possibly none of them if the kernel is
booted on a non-sunxi platform. These CCU drivers are relatively large;
32-bit drivers have 30-50k of data each, while the 64-bit ones are
50-75k due to the increased pointer overhead. About half of that data
comes from relocations. Let's allow the user to build these drivers as
modules so only the necessary data is loaded.
As a first step, convert the CCUs that are already platform drivers.
When the drivers are built as modules, normally the file name becomes
the module name. However, the current file names are inconsistent with
the <platform>-<peripheral> name used everywhere else: the devicetree
bindings, the platform driver names, and the Kconfig symbols. Use
Makfile logic to rename the modules so they follow the usual pattern.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211119033338.25486-3-samuel@sholland.org
For the individual CCU drivers to be built as modules, the ops structs,
helper functions, and callback registration functions must be exported.
These symbols are intended for use only by the adjacent CCU drivers, so
export them into the SUNXI_CCU namespace.
of_sunxi_ccu_probe is not exported because it is only used by built-in
OF clock providers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211119033338.25486-2-samuel@sholland.org
The macro p_to_snd_cx18_card() is just a variant for container_of(),
not actually used inside the code. So, drop it.
This address a clang warning.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
The macro p_to_snd_ivtv_card() is just a variant for container_of(),
not actually used inside the code. So, drop it.
This address a clang warning.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This function is defined twice, one at cx25821-i2c and the other
inside cx25821-core. It turns that only the first
is actually used inside the code.
This causes a clang warning.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
The G2 decoder block produces NV12 4x4 tiled format (NV12_4L4).
Enable the G2 post-processor block, in order to produce regular NV12.
The logic in hantro_postproc.c is leveraged to take care of allocating
the extra buffers and configure the post-processor, which is
significantly simpler than the one on the G1.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
The struct is not used outside this file, so it can be static.
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
VeriSilicon Hantro G2 core supports other codecs besides hevc.
Factor out some common code in preparation for vp9 support.
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
