Use dev_err() rather than pr_err() to display the error message.
pinctrl_dev_get_name(pctldev) is no longer necessary because
dev_err() shows which device the message is related to.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use dev_err() rather than pr_err() to display the error message.
(Besides, dev_err() is already used 7 lines below in this function.)
Also, drop the redundant information "on %s" because dev_err() shows
which device the message is related to.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some device present proprietary collections with a usage min of 0x00 and
a usage max of 0xffff. hid-core currently reject them while most of the
time this is harmless.
Let's ignore the exceeding usages, and hope for the best.
Reported-by: Simon Wörner <mail@simon-woerner.de>
Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Signed-off-by: Jiri Kosina <jkosina@suse.com>
This variable is used as an iterator and initialized in the
list_for_each() loop.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Clean-up omap4_local_timer_init to drop deal legacy code
- Provide proper IO map table for dra7
- Clean-up IOMMU layer init code as it now uses IOMMU framework
- A series of changes to fix up dm814x support that's been in a broken
half-merged state for quite some time
- A series of PRCM and hwmod changes via Paul Walmsley <paul@pwsan.com>:
- I/O wakeup support for AM43xx
- register lock and unlock support to the hwmod code (needed for the RTC
IP blocks on some chips)
- several fixes for sparse warnings and an unnecessary null pointer test
- a DRA7xx clockdomain configuration workaround, to deal with some hardware
bugs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVsc29AAoJEBvUPslcq6VzLNkQALzsnwliV3Q8x5qGOyOfm6Wf
N5KKG94iwcfSf2P6xDP9n3H0xgG9LNK5jQn5kXRdXl1R2eZwPuMiuSXJVEErwZY2
tMH+1lRYieyioLOzHAsuvNNbcB5UAY33jHtip5ofi6STaRocc5BMl0dhuUAusRcG
Qmso5zsiA04KKQqI3JWZkWFRyPX89SLMXOHnFXdKqAWSh1n+tCmSh+cO/EqAluPZ
X89mUldJESaLXR4xdAGRNthDQ68T78PTHX2GcCi2F6IGMwgdwOBqVid65gg8Ewac
bDEX+ZK32+sQxAmd+VtJCVXw6TnumnWSlTGH1xTwmRIfBmgWr4tQfu8b9INfloei
YjZYzBmWVR4SeWeATO1a/qP9snjtjlzxJ+34fzWndFq4eeM9YkF0lH53dbCnxlYp
TJnEOHFJdMOQVKxClME5n9ds1y7/K/p+jCwUrAF9z3wxiSms9RImvFroWPI54uzr
NEdduyetJLthhxTVaICT4K6ay8gouJvcjY3R8Xp0b2f5szdaxGmGqnVJynGL4fdU
CFY1orgJLS4Em50phOZZpjaSla2A2uAz79zQlFt6mr71uKeSzRXTXsOczAheyR0M
5UGqFOs1X2uqFctlGmacrTTgyxhtueOCG7R/kQ5oLHB6R39Tm07PeomGreG9Fznm
1Ylbo1BeYHn3rsSkCLfi
=1coy
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.3/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
SoC changes for omaps for v4.3 merge window:
- Clean-up omap4_local_timer_init to drop deal legacy code
- Provide proper IO map table for dra7
- Clean-up IOMMU layer init code as it now uses IOMMU framework
- A series of changes to fix up dm814x support that's been in a broken
half-merged state for quite some time
- A series of PRCM and hwmod changes via Paul Walmsley <paul@pwsan.com>:
- I/O wakeup support for AM43xx
- register lock and unlock support to the hwmod code (needed for the RTC
IP blocks on some chips)
- several fixes for sparse warnings and an unnecessary null pointer test
- a DRA7xx clockdomain configuration workaround, to deal with some hardware
bugs
* tag 'omap-for-v4.3/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: OMAP2: Add minimal dm814x hwmod support
ARM: OMAP2+: Prepare dm81xx hwmod code for adding minimal dm814x support
ARM: PRM: AM437x: Enable IO wakeup feature
ARM: OMAP4+: PRM: Add AM437x specific data
ARM: OMAP: PRM: Remove hardcoding of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 register offsets
ARM: dts: AM4372: Add PRCM IRQ entry
ARM: AM43xx: Add the PRM IRQ register offsets
ARM: OMAP4: PRM: Remove hardcoding of PRM_IO_PMCTRL_OFFSET register
ARM: OMAP2+: Add support for initializing dm814x clocks
ARM: OMAP2+: Add custom prwdm_operations for 81xx to support dm814x
ARM: OMAP2+: Add minimal clockdomains for dm814x
ARM: OMAP2+: Fix scm compatible for dm814x
ARM: OMAP2+: Fix dm814x DT_MACHINE_START
ARM: OMAP2+: Remove module references from IOMMU machine layer
ARM: DRA7: Provide proper IO map table
ARM: OMAP2+: Clean up omap4_local_timer_init
ARM: OMAP2: Delete an unnecessary check
ARM: OMAP2+: sparse: add missing function declarations
ARM: OMAP2+: sparse: add missing static declaration
ARM: OMAP2+: hwmod: add support for lock and unlock hooks
...
Signed-off-by: Olof Johansson <olof@lixom.net>
We should release "sd" before returning.
Fixes: 0fa12ad1b285 ('ext4: Handle error from dquot_initialize()')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Jan Kara <jack@suse.com>
* Add Audio MIX and CTU support to r8a779[01] SoCs
* Correct IRQ sense for adv7511 on lager board
* Add sound label to koelsch and lager boards
* Add IIC support to emev2 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVsfDJAAoJENfPZGlqN0++97QP/3aAapMZDRh/JH6pwUZRuAFG
Y++xqO8VacSmhw8MzvLrSd9st2aaje3KEM+z0a8Fs7BrWfcqBROJFHH2o6scotYS
Q+d+SCv1zDAokJrmwtooXzn6q6JPd+GgBW1y+r3YmPy1zduMbcbHK0/lk9OyKFGD
7Ei/zVs1EBXVEALVvwAD1/fCX2htPh08/9pkHKXGMSRcMDaTzqA9JMKimxas4sH3
S0sv6fC6ZrinJf26VW3HHvnrCcaFwG69aTdd4mo/qTIlZEeEqbYLQ+Hr9I+G+xBR
L+XZuyP9bJ2InbmQxMXPw86yrCiDckMHzXvL+FVfHGJmXc7i/xwDcSg5VCzZnBlc
zm0+X/qKkhLY579eCresjhImg4GOodTKJgQaGjJom4SgjdzlU8vzwMK/6GIhFvVR
7DEIVatCVL2PsRUbhhgJFh1keLKgFJhbRDkE8jl2YvxA5nmSFoGGjSB6j9t/UiNH
cKN4vVfUaD3mLcu2zoCtKHzFHdaxScNM/E84+NhEBQWj63Hi3b7osEeoHpgE96Dm
+1aFpf/RAkY7gu86l16YfTV47R1J+SiNNHXPNRivCmwEvCesD07mqm8LIMu2TYIN
zXdNwpv9Fj1DWLO6nt+iEvKRCh0SSkjkNq9TtG+33gM5+098JXLVOXw85HzgZP/g
1zGyFPYcQ6uNM5DX0BBL
=wbDB
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt2-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Second Round of Renesas ARM Based SoC DT Updates for v4.3
* Add Audio MIX and CTU support to r8a779[01] SoCs
* Correct IRQ sense for adv7511 on lager board
* Add sound label to koelsch and lager boards
* Add IIC support to emev2 SoC
* tag 'renesas-dt2-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791: Add Audio MIX support on DTSI
ARM: shmobile: r8a7791: Add Audio CTU support on DTSI
ARM: shmobile: r8a7790: Add Audio MIX support on DTSI
ARM: shmobile: r8a7790: Add Audio CTU support on DTSI
ARM: shmobile: lager: Fix adv7511 IRQ sensing
ARM: shmobile: koelsch: add sound label on DTS
ARM: shmobile: lager: add sound label on DTS
ARM: shmobile: emev2: kzm9d: enable IIC busses
ARM: shmobile: emev2: add IIC cores to dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
Highlights:
-----------
- Add RCC clocks support to STM32F429
- Add STM32429i-EVAL board support
- Use stdout-path instead of linux,stdout-path in Disco board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVsHlOAAoJEMo4jShGhw+JzIgQAIndmciWCpT383ulXawm6Mwy
lxD/8VdTG97kQJQFswaKlw0AhY8/cGH/9ZF2gHaTtqGNqT4gHCD0+4QVlOuEbH9x
p72dA3fJstYCUuSg0WcZLfHs1xkcJyYO7burpGVxy/8FhMogryqhlbPCMUKUFaSi
V2Jid69PmWhuiIvFXSp4y94hyvvcgFWxxdBi4ygWLG34n1OvzDmxOiDCqvd/Zx6n
YBMEeXPvIInfqfAsY1uS25MkpSsL+mdK4CuBmpdKqZaDOfQcHB8ioe+9F0Y1WoLx
AMLvEnPRnXMNeQ7nrAGMgWM0IsqmUj6GecJNhJdxg2iYYS6CTZmnVHWtp+chffGC
gFDKDp+BLhy0MoQwhYCVRIXJVSrIRD+tq273SCq8fd8irtHFB9B6AvfyRonVIqyk
7S5sSWVW4jPVJs9OBcnrhoVY0uteQPRhKA046vPZMaNVWrWKPft5s0oNRvq5PEjT
DBeXA2j+XZYNwUMz2JFsEfStQCDC0VJ04LxvsSr2iBVAvZCzBpFBJKe3GZl9YEbD
BWTIrc0DQ9ZsKt+wgzmPD0WI3QcPYGr3LmR3JoNMs4aQ5DBeit7rDeDivK5CRrpN
qafD17pIICMnt+xdXsNb8aThgKEHAbIe9U++Hb1lAKqbyPu5alYUzrL/k4UIXTeK
kBMMPsDKvoKB79CQidfx
=FWox
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v4.3-1b' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/dt
STM32 DT updates for v4.3, round 1.
Highlights:
-----------
- Add RCC clocks support to STM32F429
- Add STM32429i-EVAL board support
- Use stdout-path instead of linux,stdout-path in Disco board
* tag 'stm32-dt-for-v4.3-1b' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: dts: Use stdout-path in STM32F429 Discovery board
ARM: dts: Add STM32429i-EVAL board support
ARM: dts: stm32f429: Adopt STM32F4 clock driver
Signed-off-by: Olof Johansson <olof@lixom.net>
Add a few atomic_t tests, gets some compile coverage for the new
operations.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Replace the deprecated atomic_{set,clear}_mask() usage with the now
ubiquous atomic_{or,andnot}() functions.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Move the now generic definitions of atomic_{set,clear}_mask() into
linux/atomic.h to avoid endless and pointless repetition.
Also, provide an atomic_andnot() wrapper for those few archs that can
implement that.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
For tilegx, these are relatively straightforward; the architecture
provides atomic "or" and "and", both 32-bit and 64-bit. To support
xor we provide a loop using "cmpexch".
For the older 32-bit tilepro architecture, we have to extend
the set of low-level assembly routines to include 32-bit "and",
as well as all three 64-bit routines. Somewhat confusingly,
some 32-bit versions are already used by the bitops inlines, with
parameter types appropriate for bitops, so we have to do a bit of
casting to match "int" to "unsigned long".
Signed-off-by: Chris Metcalf <cmetcalf@ezchip.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1436474297-32187-1-git-send-email-cmetcalf@ezchip.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Also rework the atomic implementation in terms of CPP macros to avoid
the typical repetition -- I seem to have missed this arch the last
time around when I did that.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Mostly complete rewrite of the FRV atomic implementation, instead of
using assembly files, use inline assembler.
The out-of-line CONFIG option makes a bit of a mess of things, but a
little CPP trickery gets that done too.
FRV already had the atomic logic ops but under a non standard name,
the reimplementation provides the generic names and provides the
intermediate form required for the bitops implementation.
The slightly inconsistent __atomic32_fetch_##op naming is because
__atomic_fetch_##op conlicts with GCC builtin functions.
The 64bit atomic ops use the inline assembly %Ln construct to access
the low word register (r+1), afaik this construct was not previously
used in the kernel and is completely undocumented, but I found it in
the FRV GCC code and it seems to work.
FRV had a non-standard definition of atomic_{clear,set}_mask() which
would work types other than atomic_t, the one user relying on that
(arch/frv/kernel/dma.c) got converted to use the new intermediate
form.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
TODO: use inline asm or at least asm macros to collapse the lot.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Acked-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Clean up the #ifdef guards a bit to prepare for architectures to
supply their own logic ops.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
In order to ease the debugging, add a name to the irq_chips.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The current code uses some custom variable affectations, while we have
common functions to do exactly that. Move to the common functions.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cryptsetup moved to gitlab. This is a leftover from commit e44f23b32d
(dm crypt: update URLs to new cryptsetup project page, 2015-04-05).
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Mike Snitzer <snitzer@redhat.com>
static analysis by cppcheck has found a check on alloc_bitset that
always evaluates as false and hence never finds an allocation failure:
[drivers/md/dm-cache-policy-smq.c:1689]: (warning) Logical conjunction
always evaluates to false: !EXPR && EXPR.
Fix this by removing the incorrect mq->cache_hit_bits check
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Mike Snitzer <snitzer@redhat.com>
A recent fix to the shadow timestamp inadvertly broke the running time
accounting.
We must not update the running timestamp if we fail to schedule the
event, the event will not have ran. This can (and did) result in
negative total runtime because the stopped timestamp was before the
running timestamp (we 'started' but never stopped the event -- because
it never really started we didn't have to stop it either).
Reported-and-Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Fixes: 72f669c008 ("perf: Update shadow timestamp before add event")
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org # 4.1
Cc: Shaohua Li <shli@fb.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The gpio controller on MPC5125 is identical to the MPC5121 register
wise, the only difference is that the lines 0..3 are input only instead
of 28..31 on MPC5121.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
