Commit graph

64,840 commits

Author SHA1 Message Date
Sascha Hauer
60aac93283 ARM: 7020/1: Check for multiple zreladdrs
Without CONFIG_AUTO_ZRELADDR being set the kernel needs a single
zreladdr for building zImages. Bail out if we detect multiple
zreladdrs without CONFIG_AUTO_ZRELADDR.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:40 +01:00
Stephen Boyd
3f8e288033 ARM: 7006/1: Migrate to asm-generic wrapper support
With d8ecc5c (kbuild: asm-generic support, 2011-04-27) we can
remove a handful of asm-generic wrappers in ARM code. Since the
generic version of sizes.h doesn't contain SZ_48M, we replace
the 4 users of SZ_48M with the equivalent SZ_32M + SZ_16M.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Acked-by: Krzysztof Halasa <khc@pm.waw.pl>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:40 +01:00
Barry Song
91c2ebb90b ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode
we save the l2x0 registers at the first initialization, and platform codes
can get them to restore l2x0 status after wakeup.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:51 +01:00
Barry Song
74d41f39a9 ARM: 7090/1: CACHE-L2X0: filter start address can be 0 and is often 0
this patch fixes the error in Rob Herring's
ARM: 7009/1: l2x0: Add OF based initialization
http://www.spinics.net/lists/arm-kernel/msg131123.html
it has been in rmk/for-next with commit 41c86ff5b

Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Rob Herring <robherring2@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:40 +01:00
Barry Song
1caf30924f ARM: 7089/1: L2X0: add explicit cpu_relax() for busy wait loop
using cpu_relax in busy loops is a well-known idiom in the kernel.
It's more for documentation purposes than technically needed here.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:36 +01:00
Rob Herring
8c369264b6 ARM: 7009/1: l2x0: Add OF based initialization
This adds probing for ARM L2x0 cache controllers via device tree. Support
includes the L210, L220, and PL310 controllers. The binding allows setting
up cache RAM latencies and filter addresses (PL310 only).

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:30 +01:00
Will Deacon
f73765fcb8 ARM: 7116/1: debug: provide dummy default option for DEBUG_LL UART choice
Defaulting to DEBUG_ICEDCC will cause systems to hang during boot unless
a hardware debugger is listening to the debug comms. channel.

This patch adds a dummy UART option as the default DEBUG_LL choice which
requires the platform to do the right thing.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Stephen Boyd
6996f425e5 ARM: 7097/1: debug: Move DEBUG_ICEDCC into the DEBUG_LL choice
DEBUG_ICEDCC support is just another DEBUG_LL choice and
selecting it along with other DEBUG_LL options doesn't make
much sense. Put it into the DEBUG_LL choice to avoid confusion.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Stephen Boyd
164acf96a9 ARM: 7096/1: debug: Add UART1 config choices
ARM patch 7072/1 (debug: use kconfig choice for selecting
DEBUG_LL UART) didn't notice that the Kconfigs relied on being
unselected to configure a different serial port. Since there is
no NONE option in a choice menu, explicitly add the other option
so that both serial ports can be selected.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Will Deacon
4f5ef9226a ARM: 7073/1: debug: augment DEBUG_LL Kconfig help to clarify behaviour
Enabled DEBUG_LL hardcodes the UART address into the kernel and results
in a non-portable kernel image. Since this option is only intended for
use when debugging early boot failures, supporting multiple platforms
in such a configuration is not the intended use-case.

This patch documents this limitation in the DEBUG_LL Kconfig help text,
so that users are aware of the portability restrictions that are associated
with enabling low-level debugging support.

Reported-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Will Deacon
17916b284e ARM: 7072/1: debug: use kconfig choice for selecting DEBUG_LL UART
Enabling CONFIG_DEBUG_LL (which is required for earlyprintk) hardwires
the debug UART address into the kernel, so that we can print before the
platform is initialised.

If the user inadvertently selects multiple platforms with DEBUG_LL
enabled, the UART address may not be correct and will likely cause the
kernel to hang in the very early stages of boot.

This patch, based on a skeleton from Russell, uses a Kconfig choice for
selecting the DEBUG_LL UART, therefore allowing the user to make a
choice about the supported platform when DEBUG_LL is enabled.

Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Jamie Iles
5a567d78c4 ARM: 7115/4: move __exception and friends to asm/exception.h
The definition of __exception_irq_entry for
CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a
circular dependency with it's current home in asm/system.h. Create
asm/exception.h and update all current users.

v4:	- rebase to rmk/for-next
v3:	- remove redundant includes of linux/ftrace.h
v2:	- document the usage restricitions of __exception*

Cc: Zoltan Devai <zdevai@gmail.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:44 +01:00
Shawn Guo
0af8aa0069 ARM: 7124/1: smp: Add a localtimer handler callable from C code
In order to be able to handle localtimer directly from C code instead of
assembly code, introduce handle_local_timer(), which is modeled after
handle_IRQ().

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:44 +01:00
Shawn Guo
0b5a1b95dc ARM: 7123/1: smp: Add an IPI handler callable from C code
In order to be able to handle IPI directly from C code instead of
assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Shawn Guo
26a527e69d ARM: 7100/1: smp_scu: remove __init annotation from scu_enable()
When Cortex-A9 MPCore resumes from Dormant or Shutdown modes,
SCU needs to be re-enabled.  This patch removes __init annotation
from function scu_enable(), so that platform resume procedure can
call it to re-enable SCU.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Will Deacon
267840f339 ARM: 7061/1: gic: convert logical CPU numbers into physical numbers
The GIC driver must convert logical CPU numbers passed in from Linux
into physical CPU numbers that are understood by the hardware.

This patch uses the new cpu_logical_map macro for performing the
conversion inside the GIC driver.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Will Deacon
d6257288c4 ARM: 7060/1: smp: populate logical CPU mapping during boot
To allow booting Linux on a CPU with physical ID != 0, we need to
provide a mapping from the logical CPU number to the physical CPU
number.

This patch adds such a mapping and populates it during boot.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Vincent Guittot
c9018aab8e ARM: 7011/1: Add ARM cpu topology definition
The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and sched_smt.

The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.

Changes since v4 :
*  Remove unnecessary parentheses and blank lines

Changes since v3 :
* Update the format of printk message
* Remove blank line

Changes since v2 :
* Update the commit message and some comments

Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Martin Schwidefsky
85055dd805 PM / Hibernate: Include storage keys in hibernation image on s390
For s390 there is one additional byte associated with each page,
the storage key. This byte contains the referenced and changed
bits and needs to be included into the hibernation image.
If the storage keys are not restored to their previous state all
original pages would appear to be dirty. This can cause
inconsistencies e.g. with read-only filesystems.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2011-10-16 23:27:46 +02:00
Linus Torvalds
8bc03e8f3a Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm:
  ARM: 7128/1: vic: Don't write to the read-only register VIC_IRQ_STATUS
  ARM: 7122/1: localtimer: add header linux/errno.h explicitly
  ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
  ARM: 7113/1: mm: Align bank start to MAX_ORDER_NR_PAGES
2011-10-16 13:08:27 -07:00
Zoltan Devai
f8be12d153 ARM: 7128/1: vic: Don't write to the read-only register VIC_IRQ_STATUS
This is unneeded and causes an abort on the SPMP8000 platform.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Zoltan Devai <zoss@devai.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-15 11:04:22 +01:00
Shawn Guo
bb1ac3ec95 ARM: 7122/1: localtimer: add header linux/errno.h explicitly
Per the text in  Documentation/SubmitChecklist as below, we should
explicitly have header linux/errno.h in localtimer.h for ENXIO
reference.

1: If you use a facility then #include the file that defines/declares
   that facility.  Don't depend on other header files pulling in ones
   that you use.

Otherwise, we may run into some compiling error like the following one,
if any file includes localtimer.h without CONFIG_LOCAL_TIMERS defined.

  arch/arm/include/asm/localtimer.h: In function ‘local_timer_setup’:
  arch/arm/include/asm/localtimer.h:53:10: error: ‘ENXIO’ undeclared (first use in this function)

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-15 11:04:22 +01:00
Will Deacon
29a541f6c1 ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
Using COHERENT_LINE_{MISS,HIT} for cache misses and references
respectively is completely wrong. Instead, use the L1D events which
are a better and more useful approximation despite ignoring instruction
traffic.

Reported-by: Alasdair Grant <alasdair.grant@arm.com>
Reported-by: Matt Horsnell <matt.horsnell@arm.com>
Reported-by: Michael Williams <michael.williams@arm.com>
Cc: stable@kernel.org
Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-15 11:04:22 +01:00
Florian Tobias Schandinat
ef26b7943c Merge branch 'for-florian' of git://gitorious.org/linux-omap-dss2/linux into fbdev-next 2011-10-15 00:19:52 +00:00
Florian Tobias Schandinat
07aaae44f5 Merge commit 'v3.1-rc9' into fbdev-next 2011-10-15 00:14:01 +00:00
Jan Beulich
72da0b07b1 x86: constify PCI raw ops structures
As with any other such change, the goal is to prevent inadvertent
writes to these structures (assuming DEBUG_RODATA is enabled), and to
separate data (possibly frequently) written to from such never getting
modified.

Reviewed-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-14 09:05:28 -07:00
Andi Kleen
30963c0ac7 x86, intel: Use c->microcode for Atom errata check
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-10-14 13:16:38 +02:00
Andi Kleen
506ed6b53e x86, intel: Output microcode revision in /proc/cpuinfo
I got a request to make it easier to determine the microcode
update level on Intel CPUs. This patch adds a new "microcode"
field to /proc/cpuinfo.

The microcode level is also outputed on fatal machine checks
together with the other CPUID model information.

I removed the respective code from the microcode update driver,
it just reads the field from cpu_data. Also when the microcode
is updated it fills in the new values too.

I had to add a memory barrier to native_cpuid to prevent it
being optimized away when the result is not used.

This turns out to clean up further code which already got this
information manually. This is done in followon patches.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-10-14 13:16:35 +02:00
Peter Zijlstra
84ac218f02 microblaze: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW usage
As far as I can tell the only reason microblaze has
__ARCH_WANT_INTERRUPTS_ON_CTXSW is because it initializes new task state
with interrupts enabled so that on switch_to() interrupts get enabled.

So change copy_thread() to clear MSR_IE instead of set it, this will
ensure switch_to() will always keep IRQs disabled.

The scheduler will disable IRQs when taking rq->lock in schedule() and
enable IRQs in finish_lock_switch() after its done its magic.

This leaves ARM the only __ARCH_WANT_INTERRUPTS_ON_CTXSW user.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:28:42 +02:00
Michal Simek
cb5edfe3e5 microblaze: Use delay slot in __strnlen_user, __strncpy_user
Use delay slot to speedup if maxlen is zero.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:34 +02:00
Michal Simek
90fcf38363 microblaze: Remove NET_IP_ALIGN from system.h
Use default value (which is the same) from
include/linux/skbuff.h.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:33 +02:00
Michal Simek
c8ae8a8208 microblaze: Add __ucmpdi2() helper function
Add missing __ucmpdi2 helper function.

Error log:
kernel/built-in.o: In function `print_graph_duration':
: undefined reference to `__ucmpdi2'
kernel/built-in.o: In function `print_graph_duration':
: undefined reference to `__ucmpdi2'

Based on MIPS code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:32 +02:00
Edgar E. Iglesias
15ec090833 microblaze: Raise SIGFPE/FPE_INTDIV for div by zero
It fixes the signal nr raised for divizion by zero from
SIGILL to SIGFPE, in accordance to POSIX and other archs.

This came up due to a failed test in the GCC testsuite.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-10-14 12:24:31 +02:00
Edgar E. Iglesias
69515f8b95 microblaze: Switch ELF_ARCH code to 189
Switch arch code to 189, the registered code in the upstream
version of binutils. Continue to accept the experimental 0xbaab.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:31 +02:00
Eli Billauer
0fb2a6f283 microblaze: Added DMA sync operations
Added support gor dma_direct_sync_single_for_*() and dma_direct_sync_sg_for_*()

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:30 +02:00
Eli Billauer
cf560c1801 microblaze: Moved __dma_sync() to dma-mapping.h
__dma_sync_page() was replaced by __dma_sync(), and parameters of calls to
the new function were adjusted to match __dma_sync()'s format.

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:29 +02:00
Michal Simek
2309f7cfca microblaze: Add PVR for Microblaze v8.20.a
Microblaze v8.20.a has 0x15 version string.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:28 +02:00
Michal Simek
41b7602ed1 microblaze: Fix access_ok macro
There is the problem with bit OR (|) because for
some combination is addr | size | addr+size equal
to seq.

For standard kernel setting (kernel starts at 0xC0000000)
is seq for user space 0xBFFFFFFF and everything below
this limit is fine.

But even address 0xBFFFFFFF is fine because it
is below kernel space.

Signed-off-by: Andrew Fedonczuk <andrew.fedonczuk@ericsson.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:27 +02:00
Michal Simek
ebe211254b microblaze: Add loop unrolling for PAGE in copy_tofrom_user
Increase performance by loop unrolling.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:26 +02:00
Michal Simek
782d491fc2 microblaze: Simplify logic for unaligned byte copying
Save jump instruction for unaligned byte copying.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:25 +02:00
Michal Simek
c83858b3e6 microblaze: Change label names - copy_tofrom_user
Change label name to be prepared for loop unrolling.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:22 +02:00
Michal Simek
eedac7914d microblaze: Separate fixup section definition
Move fixups below appropriate code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:22 +02:00
Michal Simek
9b133f8d87 microblaze: Change label name in copy_tofrom_user
Use label 0: for zero length copying and fixups.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:21 +02:00
Michal Simek
9c6f6f549f microblaze: Clear top bit from cnt32_to_63
Top bit is used as garbage and it must be clear
explicitly.
It is causing the problem with soft lookup code
because it checks delays which are long when
top bit is setup.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-14 12:24:20 +02:00
Timur Tabi
2bcd1c0cfc powerpc/fsl_msi: add support for "msi-address-64" property
Add support for the msi-address-64 property of a PCI node.  This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).

In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly.  These fields are replace with a single field, msiir_offset,
to reflect the new meaning.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-14 02:54:29 -05:00
Sascha Hauer
c5d7a9230e Merge branch 'features/denx-mx28' into for-arnd-features 2011-10-14 09:37:34 +02:00
Sascha Hauer
d546029043 Merge branch 'features/ahci' into for-arnd-features 2011-10-14 09:37:27 +02:00
Axel Lin
ec4f5423b5 ARM: S3C2443: Remove redundant s3c_register_clocks call for init_clocks
Since commit af337f3e63
"ARM: S3C2443: Move parts of the clock code to common clock file",
the init_clocks array is moved to arch/arm/plat-s3c24xx/s3c2443-clock.c.
Now we call s3c_register_clocks for init_clocks in s3c2443_common_init_clocks.

Thus we can remove the empty init_clocks array here and remove the
redundant s3c_register_clocks call for init_clocks in s3c2443_init_clocks.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-10-14 15:41:36 +09:00
Heiko Stuebner
5227a54a0f ARM: S3C24XX: Add devname for hsmmc1 pclk
S3C2443 uses hsmmc1 as its only hsmmc device and for S3C2416/S3C2450
it's the second hsmmc channel with the same PCLKCON bit.
The hsmmc-if clocks on both systems already got a devname, as did
the hsmmc pclk for hsmmc0 on the S3C2416. So to make it possible to
identify the hsmmc1 pclk on S3C2416 add the correct devname for it.
The sclk name on S3C2443 also is s3c-sdhci.1.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-10-14 15:35:08 +09:00
Heiko Stuebner
33ccedfd1b ARM: S3C24XX: use clk_get_rate to init fclk in common_setup_clocks
Previously the fclk rate was calculated by dividing the pll through
the divider value of the armdiv. With a real armdiv clk in place it's
possible to simply read its value, which does essentially the same.

This change makes the whole fdiv_fn function pointers supplied to
s3c2443_common_init_clocks and s3c2443_common_setup_clocks
obsolete, so remove it too.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-10-14 15:15:53 +09:00