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1,267,977 commits

Author SHA1 Message Date
Bjorn Andersson
6514b6efdd Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into clk-for-6.8
Merge SM8650 GCC, TCSRCC, DISPCC, GPUCC and RPMHCC bindings through a
topic branch to make it possible to also merge and use the constants in
the DeviceTree branch.
2023-12-07 08:08:54 -08:00
Neil Armstrong
873f224403 dt-bindings: clock: qcom: Document the SM8650 RPMH Clock Controller
Add bindings documentation for the SM8650 RPMH Clock Controller.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:08:30 -08:00
Neil Armstrong
a0aa7fa5c3 dt-bindings: clock: qcom: document the SM8650 GPU Clock Controller
Add bindings documentation for the SM8650 Graphics Clock Controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-4-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:07:47 -08:00
Neil Armstrong
c1120359d4 dt-bindings: clock: qcom: document the SM8650 Display Clock Controller
Add bindings documentation for the SM8650 Display Clock Controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-3-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:07:47 -08:00
Neil Armstrong
b69d932154 dt-bindings: clock: qcom: document the SM8650 General Clock Controller
Add bindings documentation for the SM8650 General Clock Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-2-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:07:47 -08:00
Neil Armstrong
1a3b3bd142 dt-bindings: clock: qcom: document the SM8650 TCSR Clock Controller
Add bindings documentation for the SM8650 TCSR Clock Controller.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-1-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:07:46 -08:00
Biju Das
9b413e3c07 mfd: da9062: Simplify obtaining I2C match data
Simplify probe() by replacing of_device_get_match_data() and ID lookup for
retrieving match data by i2c_get_match_data().

Some minor cleanups:
 * Remove the trailing comma in the terminator entry for the ID
   table making code robust against (theoretical) misrebases or other
   similar things where the new entry goes _after_ the termination without
   the compiler noticing.
 * Move OF table near to the user.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231204124507.124758-1-biju.das.jz@bp.renesas.com
Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07 16:06:30 +00:00
Neil Armstrong
7a280fec21 soc: qcom: llcc: Add configuration data for SM8650
Add Last Level Cache Controller support for the SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-llcc-v2-2-f281cec608e2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:05:17 -08:00
Neil Armstrong
8fa41c40a1 dt-bindings: cache: qcom,llcc: Document the SM8650 Last Level Cache Controller
Document the Last Level Cache Controller on the SM8650 platform.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-llcc-v2-1-f281cec608e2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:05:17 -08:00
Kunwu Chan
41673c66b3 mfd: syscon: Fix null pointer dereference in of_syscon_register()
kasprintf() returns a pointer to dynamically allocated memory
which can be NULL upon failure.

Fixes: e15d7f2b81 ("mfd: syscon: Use a unique name with regmap_config")
Signed-off-by: Kunwu Chan <chentao@kylinos.cn>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20231204092443.2462115-1-chentao@kylinos.cn
Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07 16:05:11 +00:00
Vincent Knecht
8f799d304c clk: qcom: gcc-msm8939: Add missing CSI2 related clocks
When adding in the indexes for this clock-controller we missed
GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK,
GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK.

Add them in now and rename ftbl_gcc_camss_csi0_1_clk
to account for csi2 also using it.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20231029061948.505883-2-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:04:41 -08:00
Vincent Knecht
3f373de6da dt-bindings: clock: qcom,gcc-msm8939: Add CSI2 related clocks
When adding in the indexes for this clock-controller we missed
GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK,
GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK.

Add them in now.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231029061948.505883-1-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:04:40 -08:00
Bryan O'Donoghue
9bd07f2c55 arm64: dts: qcom: sc8280xp: Add in CAMCC for sc8280xp
Add in CAMCC for sc8280xp. The sc8280xp Camera Clock Controller looks
similar to most of the sdmX, smX and now scX controllers.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231026105345.3376-5-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:02:42 -08:00
Bryan O'Donoghue
ff93872a9c clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC
Add the sc8280xp CAMCC driver which follows the sdm845 CAMCC lineage
with additional CCI and IFE blocks and more granular clock parentage.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20231026105345.3376-4-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:02:33 -08:00
Bjorn Andersson
7a56e64a56 Merge branch '20231026105345.3376-3-bryan.odonoghue@linaro.org' into arm64-for-6.8
Merge the SC8280XP Camera Clock Controller binding updates from the
topic branch, to gain access to clock defines to be used in DeviceTree
source.
2023-12-07 08:01:58 -08:00
Rodrigo Vivi
aa15b03185 drm/doc/rfc: Xe is using drm_exec, so mark as completed
Nothing else to be done on this front from Xe perspective.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231201042158.80009-6-rodrigo.vivi@intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2023-12-07 11:01:12 -05:00
Bjorn Andersson
3be492cf6e Merge branch '20231026105345.3376-3-bryan.odonoghue@linaro.org' into clk-for-6.8
Merge the SC8280XP Camera Clock Controller binding changes through a
topic branch to allow them to be merged and used in the DeviceTree
source branch as well.
2023-12-07 08:00:59 -08:00
Rodrigo Vivi
34e64dd192 drm/doc/rfc: Move userptr integration and vm_bind to the 'completed' section
The must-have part of the documentation was already added to the existing
/gpu/drm-vm-bind-async. The other extra discussion around GPUVM helpers
are currently active in the community. None of those discussion should
block Xe since documentation, specially around locking was completed in
a community consensus.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231201042158.80009-5-rodrigo.vivi@intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2023-12-07 11:00:58 -05:00
Bryan O'Donoghue
206cd759fb dt-bindings: clock: Add SC8280XP CAMCC
Add device tree bindings for the camera clock controller on
Qualcomm SC8280XP platform.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231026105345.3376-3-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:00:51 -08:00
Rodrigo Vivi
16805e994b drm/doc/rfc: Move Xe 'ASYNC VM_BIND' to the 'completed' section
As already indicated in this block, the consensus was already
reached out and documented as:
The ASYNC VM_BIND document </gpu/drm-vm-bind-async>

However this was item was not moved to the completed section.
Let's move and clean up the WIP block.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231201042158.80009-4-rodrigo.vivi@intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2023-12-07 11:00:51 -05:00
Bryan O'Donoghue
4ab1721694 dt-bindings: clock: Use gcc.yaml for common clock properties
Various of the camcc bindings are repeated serially. We can use
qcom,gcc.yaml to encapsulate the generic repeated patterns.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231026105345.3376-2-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 08:00:51 -08:00
Rodrigo Vivi
0e2e6c49c1 drm/doc/rfc: Mark drm_scheduler as completed
Current drm-xe-next doesn't have any drm/scheduler patch that is not
already accepted in drm-misc-next. This completed this goal with
the consensus of how the drm/scheduler fits to the fw scheduling and
the relationship between drm_gpu_scheduler and drm_sched_entity.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231201042158.80009-3-rodrigo.vivi@intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2023-12-07 11:00:42 -05:00
Matthew Brost
a85607e3cf drm/doc/rfc: Mark long running workload as complete.
No DRM scheduler changes required, drivers just return NULL in run_job
vfunc.

The rough consensus is that no helper or extra scaffolding is needed
around long-running jobs and no further changes to drm-scheduler.

At least for now. Other drivers that currently do long-running workloads
have no plat to use drm-scheduler. Besides, the current consensus is
that this solution of simply returning NULL to the run_job function should
work without extra code duplication or complication.

On top of that, this item was already a non-blocking one for upstreaming Xe,
so let's move that to the 'Completed' section and revisit the long-running
solution as a community after Xe is integrated in DRM.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231201042158.80009-2-rodrigo.vivi@intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2023-12-07 11:00:30 -05:00
Robert Marko
cec1f2ffcc dt-bindings: clock: qcom,gcc-ipq6018: split to separate schema
The Qualcomm IPQ6018 GCC clock controller has clock inputs, thus existing
gcc-other.yaml was not describing it fully so move it to a separate schema.

Fully document the allowed and required XO and sleep clock inputs, as well
as update the provided example.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231026101931.695497-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:59:24 -08:00
Yang Li
3e743b0fcb drm/mediatek: Use devm_platform_ioremap_resource()
Remove variable 'res' and convert platform_get_resource(),
devm_ioremap_resource() to a single call to
devm_platform_ioremap_resource(), as this is exactly what this function
does.

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20230412064635.41315-1-yang.lee@linux.alibaba.com/
Link: https://patchwork.kernel.org/project/dri-devel/patch/20230412064635.41315-2-yang.lee@linux.alibaba.com/
Link: https://patchwork.kernel.org/project/dri-devel/patch/20230412064635.41315-3-yang.lee@linux.alibaba.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2023-12-07 15:58:02 +00:00
Neil Armstrong
f61319e57d soc: qcom: socinfo: Add SM8650 SoC ID table entry
Add SoC Info support for the SM8650 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-socinfo-v2-2-4751e7391dc9@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:55:36 -08:00
Neil Armstrong
216382b155 dt-bindings: arm: qcom,ids: Add SoC ID for SM8650
Add the ID for the Qualcomm SM8650 SoC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-socinfo-v2-1-4751e7391dc9@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:55:36 -08:00
Su Hui
769ff5283f backlight: ili922x: Add an error code check in ili922x_write()
Clang static analyzer complains that value stored to 'ret' is never read.
Return the error code when spi_sync() failed.

Signed-off-by: Su Hui <suhui@nfschina.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Link: https://lore.kernel.org/r/20231130051155.1235972-1-suhui@nfschina.com
Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07 15:54:55 +00:00
Mukesh Ojha
44b1f64cad arm64: dts: qcom: sm8550: Enable download mode register write
Enable download mode setting for sm8550 which can help collect
ramdump for this SoC.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/1698253601-11957-4-git-send-email-quic_mojha@quicinc.com
[bjorn: Updated tcsr offset, per Mukesh correction]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:53:54 -08:00
Mukesh Ojha
1accc6031d arm64: dts: qcom: sm8350: Add TCSR halt register space
Enable download mode for sm8350 which can help collect
ramdump for this SoC.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1698253601-11957-3-git-send-email-quic_mojha@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:53:18 -08:00
Mukesh Ojha
d59653233e arm64: dts: qcom: sm8250: Add TCSR halt register space
Enable download mode for sm8250 which can help collect
ramdump for this SoC.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1698253601-11957-2-git-send-email-quic_mojha@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:53:18 -08:00
Kathiravan Thirumoorthy
a427dd16e6 arm64: dts: qcom: ipq5018: add few more reserved memory regions
Like all other IPQ SoCs, bootloader will collect the system RAM contents
upon crash for the post morterm analysis. If we don't reserve the memory
region used by bootloader, obviously linux will consume it and upon next
boot on crash, bootloader will be loaded in the same region, which will
lead to loose some of the data, sometimes we may miss out critical
information. So lets reserve the region used by the bootloader.

Similarly SBL copies some data into the reserved region and it will be
used in the crash scenario. So reserve 1MB for SBL as well.

While at it, enable the SMEM support along with TCSR mutex.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231025-ipq5018-misc-v1-1-7d14fde97fe7@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:52:24 -08:00
Kathiravan Thirumoorthy
63a021f52f arm64: dts: qcom: ipq5332: add missing properties to the GPIO LED node
Add the color and function property to the GPIO LED node, which are
missed out in the initial submission.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231025-ipq5332-gpio-led-v1-1-0f0f52617648@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:52:08 -08:00
Kathiravan Thirumoorthy
2928212b6e arm64: dts: qcom: ipq9574: enable GPIO based LED
Add support for wlan-2g LED on GPIO64.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231025-ipq9574-led-v2-1-59b2725697ad@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:51:53 -08:00
Caleb Connolly
e0cee8dc67 arm64: dts: qcom: qrb2210-rb1: use USB host mode
The default for the QCM2290 platform that this board is based on is OTG
mode, however the role detection logic is not hooked up for this board
and the dwc3 driver is configured to not allow role switching from
userspace.

Force this board to host mode as this is the preferred usecase until we
get role switching hooked up.

Fixes: e187719613 ("arm64: dts: qcom: Add initial QTI RB1 device tree")
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231025-b4-rb1-usb-host-v1-1-522616c575ef@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:51:34 -08:00
Dmitry Baryshkov
4db09e7b96 soc: qcom: pmic_glink: enable UCSI by default
Now as the issue with the UCSI_GET_PDOS is worked around, enable UCSI
support for all PMIC_GLINK platforms except Qualcomm SC8180X. The
mentioned SoC has slightly different UCSI implementation, which I would
like be tested properly before enabling it.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231025115620.905538-3-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:48:46 -08:00
Dmitry Baryshkov
1d103d6af2 usb: typec: ucsi: fix UCSI on buggy Qualcomm devices
On sevral Qualcomm platforms (SC8180X, SM8350, SC8280XP) a call to
UCSI_GET_PDOS for non-PD partners will cause a firmware crash with no
easy way to recover from it. Since we have no easy way to determine
whether the partner really has PD support, shortcut UCSI_GET_PDOS on
such platforms. This allows us to enable UCSI support on such devices.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231025115620.905538-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:48:46 -08:00
Neil Armstrong
6da02af3f9 dt-bindings: firmware: qcom,scm: document SM8650 SCM Firmware Interface
Document the SCM Firmware Interface on the SM8650 Platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-bindings-scm-v1-1-f687b5aa3c9e@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:38:55 -08:00
Neil Armstrong
98e8bc43c2 dt-bindings: soc: qcom: pmic-glink: document SM8650 compatible
Document the PMIC GLINK firmware interface on the SM8650 Platform
by using the SM8550 bindings as fallback.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-bindings-pmic-glink-v1-1-0c2829a62565@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:38:32 -08:00
Neil Armstrong
8c1f28ff13 dt-bindings: soc: qcom,aoss-qmp: document the SM8560 Always-On Subsystem side channel
Document the Always-On Subsystem side channel on the SM8650 Platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-bindings-aoss-qmp-v1-1-8940621d704c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:37:58 -08:00
Jouni Högander
10690b8a49 drm/i915/display: Add intel_fb_bo_framebuffer_fini
Xe needs intel_fb_bo_framebuffer_fini for taking care of unpinning the fb
and taking reference.  In i915 this can be empty.

Also move intel_frontbuffer_get to be done after
intel_fb_bo_framebuffer_init to have reasonable sequences:

intel_fb_bo_framebuffer_init
intel_frontbuffer_get
...
intel_frontbuffer_put
intel_fb_bo_framebuffer_fini

v2: Empty function instead of define

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231207083451.2184562-1-jouni.hogander@intel.com
2023-12-07 17:31:02 +02:00
Bjorn Andersson
70b139a7af soc: qcom: stats: Express AOSS QMP module dependency
In the case that the Qualcomm Sleep stats driver is builtin and the AOSS
QMP driver is built as a module, neither the implementation nor the stub
functions are available during linking, resulting in the following
errors:

  qcom_stats.c:(.text+0x33c): undefined reference to `qmp_send'
  qcom_stats.c:(.text+0x8a0): undefined reference to `qmp_get'

Resolve this by expressing the dependency between the two modules.

Fixes: e84e61bdb9 ("soc: qcom: stats: Add DDR sleep stats")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/linux-arm-msm/202312061258.nAVYPFq2-lkp@intel.com/
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231205-qcom_stats-aoss_qmp-dependency-v1-1-8dabe1b5c32a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:22:00 -08:00
Arnd Bergmann
73380e2573 soc: qcom: stats: fix 64-bit division
Unguarded 64-bit division is not allowed on 32-bit kernels because this
is very slow. The result of trying anyway is a link failure:

arm-linux-gnueabi-ld: drivers/soc/qcom/qcom_stats.o: in function `qcom_ddr_stats_show':
qcom_stats.c:(.text+0x334): undefined reference to `__aeabi_uldivmod'

As this function is only used for debugging and not performance critical,
rewrite it to use div_u64() instead. ARCH_TIMER_FREQ is a multiple of
MSEC_PER_SEC anyway, so there is no loss in precisison.

Fixes: e84e61bdb9 ("soc: qcom: stats: Add DDR sleep stats")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20231206123717.524009-1-arnd@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07 07:21:51 -08:00
Ulf Hansson
72cd89517f mmc: Merge branch fixes into next
Merge the mmc fixes for v6.7-rc[n] into the next branch, to allow them to
get tested together with the new mmc changes that are targeted for v6.8.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-12-07 15:15:02 +01:00
Geert Uytterhoeven
1036f69e25 mmc: core: Cancel delayed work before releasing host
On RZ/Five SMARC EVK, where probing of SDHI is deferred due to probe
deferral of the vqmmc-supply regulator:

    ------------[ cut here ]------------
    WARNING: CPU: 0 PID: 0 at kernel/time/timer.c:1738 __run_timers.part.0+0x1d0/0x1e8
    Modules linked in:
    CPU: 0 PID: 0 Comm: swapper Not tainted 6.7.0-rc4 #101
    Hardware name: Renesas SMARC EVK based on r9a07g043f01 (DT)
    epc : __run_timers.part.0+0x1d0/0x1e8
     ra : __run_timers.part.0+0x134/0x1e8
    epc : ffffffff800771a4 ra : ffffffff80077108 sp : ffffffc800003e60
     gp : ffffffff814f5028 tp : ffffffff8140c5c0 t0 : ffffffc800000000
     t1 : 0000000000000001 t2 : ffffffff81201300 s0 : ffffffc800003f20
     s1 : ffffffd8023bc4a0 a0 : 00000000fffee6b0 a1 : 0004010000400000
     a2 : ffffffffc0000016 a3 : ffffffff81488640 a4 : ffffffc800003e60
     a5 : 0000000000000000 a6 : 0000000004000000 a7 : ffffffc800003e68
     s2 : 0000000000000122 s3 : 0000000000200000 s4 : 0000000000000000
     s5 : ffffffffffffffff s6 : ffffffff81488678 s7 : ffffffff814886c0
     s8 : ffffffff814f49c0 s9 : ffffffff81488640 s10: 0000000000000000
     s11: ffffffc800003e60 t3 : 0000000000000240 t4 : 0000000000000a52
     t5 : ffffffd8024ae018 t6 : ffffffd8024ae038
    status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003
    [<ffffffff800771a4>] __run_timers.part.0+0x1d0/0x1e8
    [<ffffffff800771e0>] run_timer_softirq+0x24/0x4a
    [<ffffffff80809092>] __do_softirq+0xc6/0x1fa
    [<ffffffff80028e4c>] irq_exit_rcu+0x66/0x84
    [<ffffffff80800f7a>] handle_riscv_irq+0x40/0x4e
    [<ffffffff80808f48>] call_on_irq_stack+0x1c/0x28
    ---[ end trace 0000000000000000 ]---

What happens?

    renesas_sdhi_probe()
    {
    	tmio_mmc_host_alloc()
	    mmc_alloc_host()
		INIT_DELAYED_WORK(&host->detect, mmc_rescan);

	devm_request_irq(tmio_mmc_irq);

	/*
	 * After this, the interrupt handler may be invoked at any time
	 *
	 *  tmio_mmc_irq()
	 *  {
	 *	__tmio_mmc_card_detect_irq()
	 *	    mmc_detect_change()
	 *		_mmc_detect_change()
	 *		    mmc_schedule_delayed_work(&host->detect, delay);
	 *  }
	 */

	tmio_mmc_host_probe()
	    tmio_mmc_init_ocr()
		-EPROBE_DEFER

	tmio_mmc_host_free()
	    mmc_free_host()
    }

When expire_timers() runs later, it warns because the MMC host structure
containing the delayed work was freed, and now contains an invalid work
function pointer.

Fix this by cancelling any pending delayed work before releasing the
MMC host structure.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/205dc4c91b47e31b64392fe2498c7a449e717b4b.1701689330.git.geert+renesas@glider.be
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-12-07 15:14:23 +01:00
Axe Yang
d3ddafd34b mmc: mtk-sd: Extend number of tuning steps
Previously, during the MSDC calibration process, a full clock cycle
actually not be covered, which in some cases didn't yield the best
results and could cause CRC errors. This problem is particularly
evident when MSDC is used as an SDIO host. In fact, MSDC support
tuning up to a maximum of 64 steps, but by default, the step number
is 32. By increase the tuning step, we are more likely to cover more
parts of a clock cycle, and get better calibration result.

To illustrate, when tuning 32 steps, if the obtained window has a hole
near the middle, like this: 0xffc07ff (hex), then the selected delay
will be the 6 (counting from right to left).

(32 <- 1)
1111 1111 1100 0000 0000 0111 11(1)1 1111

However, if we tune 64 steps, the window obtained may look like this:
0xfffffffffffc07ff. The final selected delay will be 44, which is
safer as it is further away from the hole:

(64 <- 1)
1111 ... (1)111 1111 1111 1111 1111 1100 0000 0000 0111 1111 1111

In this case, delay 6 selected through 32 steps tuning is obviously
not optimal, and this delay is closer to the hole, using it would
easily cause CRC problems.

As per mesaurements taken on mediatek SoC platform, the tuning phase
will take:
	eMMC	- 32 steps: ~3ms
		- 64 steps: ~6ms
	SDIO	- 32 steps: ~4ms
		- 64 steos: ~7ms
Tuning more steps won't prolong boot times by any meaningful amount
of time, so for SD/SDIO the default tuning steps will be adjust to
64. But for eMMC, it is still preferred to use 32 steps tuning as
otherwise there would be performance lose when accessing the RPMB
partition(requiring retuning each time).

You can configure property "mediatek,tuning-step" in MSDC dts node
to adjust the step number.

Signed-off-by: Axe Yang <axe.yang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231207063535.29546-3-axe.yang@mediatek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-12-07 15:13:08 +01:00
Axe Yang
ec1aaf792d dt-bindings: mmc: mtk-sd: add tuning steps related property
Add 'mediatek,tuning-steps' setting. This property will give MSDC
a chance to extend tuning steps up to 64. With more tuning steps,
MSDC may achieve a more optimal calibration result, thus avoiding
potential CRC issues.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Axe Yang <axe.yang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231207063535.29546-2-axe.yang@mediatek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-12-07 15:12:36 +01:00
Randy Dunlap
1f30f51053 mmc: sdhci-omap: don't misuse kernel-doc marker
Use "/*" instead of "/**" for common C comments to prevent warnings
from scripts/kernel-doc.

sdhci-omap.c:3: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
sdhci-omap.c:3: warning: missing initial short description on line:
 * SDHCI Controller driver for TI's OMAP SoCs

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/oe-kbuild-all/202311201117.lFxgJTK6-lkp@intel.com/
Link: https://lore.kernel.org/r/20231206055855.21092-1-rdunlap@infradead.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-12-07 15:11:51 +01:00
Dan Carpenter
d685aea5e0
ASoC: audio-graph-card2: fix off by one in graph_parse_node_multi_nm()
The > comparison should be >= to avoid writing one element beyond the end
of the dai_link->ch_maps[] array.  The dai_link->ch_maps[] array is
allocated in graph_parse_node_multi() and it has "nm_max" elements.

Fixes: e2de6808df ("ASoC: audio-graph-card2: add CPU:Codec = N:M support")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/1032216f-902f-48f9-aa49-9d5ece8e87f2@moroto.mountain
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-12-07 14:00:03 +00:00
Ulf Hansson
6fc0ca1791 mmc: Merge branch fixes into next
Merge the mmc fixes for v6.7-rc[n] into the next branch, to allow them to
get tested together with the new mmc changes that are targeted for v6.8.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-12-07 14:59:57 +01:00