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Author SHA1 Message Date
Bjorn Andersson
5602dfc37a Merge branch '20230316072940.29137-2-quic_devipriy@quicinc.com' into HEAD
Merge the IPQ9574 Global Clock Controller Devicetree binding, to make
available the clock definitions used in the Devicetree source.
2023-04-07 10:35:12 -07:00
Devi Priya
34d1a90bdb arm64: defconfig: Enable IPQ9574 SoC base configs
Enables clk & pinctrl related configs for Qualcomm IPQ9574 SoC

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-7-quic_devipriy@quicinc.com
2023-04-07 10:30:30 -07:00
Devi Priya
d75b82cff4 clk: qcom: Add Global Clock Controller driver for IPQ9574
Add Global Clock Controller (GCC) driver for ipq9574 based devices

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-3-quic_devipriy@quicinc.com
2023-04-07 10:28:15 -07:00
Bjorn Andersson
3a5c7ed3d8 Merge branch '20230316072940.29137-2-quic_devipriy@quicinc.com' into clk-for-6.4
Merge IPQ9574 Global Clock Controller binding through a topic branch to
allow it also be introduced in the Devicetree source tree.
2023-04-07 10:27:28 -07:00
Devi Priya
b065b23d3c dt-bindings: clock: Add ipq9574 clock and reset definitions
Add clock and reset ID definitions for ipq9574

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-2-quic_devipriy@quicinc.com
2023-04-07 10:27:16 -07:00
Petr Vorel
c85c8a9927 arm64: dts: qcom: msm8994-angler: removed clash with smem_region
This fixes memory overlap error:
[    0.000000] reserved@6300000 (0x0000000006300000--0x0000000007000000) overlaps with smem_region@6a00000 (0x0000000006a00000--0x0000000006c00000)

smem_region is the same as in downstream (qcom,smem) [1], therefore
split reserved memory into two sections on either side of smem_region.

Not adding labels as it's not expected to be used.

[1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm/boot/dts/qcom/msm8994.dtsi#948

Fixes: 380cd3a34b ("arm64: dts: msm8994-angler: fix the memory map")

Signed-off-by: Petr Vorel <pvorel@suse.cz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230131200414.24373-3-pvorel@suse.cz
2023-04-07 10:21:27 -07:00
Petr Vorel
fe88480a6b arm64: dts: qcom: msm8994-angler: Fix cont_splash_mem mapping
Angler's cont_splash_mem mapping is shorter in downstream [1],
therefore 380cd3a34b was wrong. Obviously also 0e5ded926f was wrong
(workaround which fixed booting at the time).

This fixes error:
[    0.000000] memory@3401000 (0x0000000003401000--0x0000000005601000) overlaps with tzapp@4800000 (0x0000000004800000--0x0000000006100000)

[1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm64/boot/dts/huawei/huawei_msm8994_angler_row_vn1/huawei-fingerprint.dtsi#16

Fixes: 380cd3a34b ("arm64: dts: msm8994-angler: fix the memory map")
Fixes: 0e5ded926f ("arm64: dts: qcom: msm8994-angler: Disable cont_splash_mem")

Signed-off-by: Petr Vorel <pvorel@suse.cz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230131200414.24373-2-pvorel@suse.cz
2023-04-07 10:21:23 -07:00
Douglas Anderson
cb5d1dd3a7 MAINTAINERS: qcom: Add reviewer for Qualcomm Chromebooks
Developers on the ChromeOS team generally want to be notified to
review changes that affect Chromebook device tree files. While we
could individually add developers, the set of developers and the time
each one has available to review patches will change over time. Let's
try adding a group list as a reviewer and see if that's an effective
way to manage things.

A few notes:
* Though this email address is actually backed by a mailing list, I'm
  adding it as "R"eviewer and not "L"ist since it's not a publicly
  readable mailing list and it's intended just to have a few people on
  it. This also hopefully conveys a little more responisbility for the
  people that are part of this group.
* I've added all sc7180 and sc7280 files here. At the moment I'm not
  aware of any non-Chromebooks being supported that use these
  chips. If later something shows up then we can try to narrow down.
* I've added "sdm845-cheza" to this list but not the rest of
  "sdm845". Cheza never shipped but some developers still find the old
  developer boards useful and thus it continues to get minimal
  maintenance. Most sdm845 device tree work, however, seems to be for
  non-Chromebooks.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230330141051.1.If8eb4f30cb53a00a5bef1b7d3cc645c3536615ec@changeid
2023-04-07 09:42:23 -07:00
Daniel Lezcano
3d439b1a2a thermal/core: Alloc-copy-free the thermal zone parameters structure
The caller of the function thermal_zone_device_register_with_trips()
can pass a thermal_zone_params structure parameter.

This one is used by the thermal core code until the thermal zone is
destroyed. That forces the caller, so the driver, to keep the pointer
valid until it unregisters the thermal zone if we want to make the
thermal zone device structure private the core code.

As the thermal zone device structure would be private, the driver can
not access to thermal zone device structure to retrieve the tzp field
after it passed it to register the thermal zone.

So instead of forcing the users of the function to deal with the tzp
structure life cycle, make the usage easier by allocating our own
thermal zone params, copying the parameter content and by freeing at
unregister time. The user can then create the parameters on the stack,
pass it to the registering function and forget about it.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230404075138.2914680-3-daniel.lezcano@linaro.org
2023-04-07 18:36:28 +02:00
Daniel Lezcano
ac614a9b4c thermal/of: Unexport unused OF functions
The functions thermal_of_zone_register() and
thermal_of_zone_unregister() are no longer needed from the drivers as
the devm_ variant is always used.

Make them static in the C file and remove their declaration from thermal.h

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230404075138.2914680-2-daniel.lezcano@linaro.org
2023-04-07 18:36:28 +02:00
Daniel Lezcano
8454c8c09c thermal/drivers/bcm2835: Remove buggy call to thermal_of_zone_unregister
The driver is using the devm_thermal_of_zone_device_register().

In the error path of the function calling
devm_thermal_of_zone_device_register(), the function
devm_thermal_of_zone_unregister() should be called instead of
thermal_of_zone_unregister(), otherwise this one will be called twice
when the device is freed.

The same happens for the remove function where the devm_ guarantee the
thermal_of_zone_unregister() will be called, so adding this call in
the remove function will lead to a double free also.

Use devm_ variant in the error path of the probe function.

Remove thermal_of_zone_unregister() in the remove function.

Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230404075138.2914680-1-daniel.lezcano@linaro.org
2023-04-07 18:36:28 +02:00
Maxime Chevallier
4a670ac3e7
regmap: allow upshifting register addresses before performing operations
Similar to the existing reg_downshift mechanism, that is used to
translate register addresses on busses that have a smaller address
stride, it's also possible to want to upshift register addresses.

Such a case was encountered when network PHYs and PCS that usually sit
on a MDIO bus (16-bits register with a stride of 1) are integrated
directly as memory-mapped devices. Here, the same register layout
defined in 802.3 is used, but the register now have a larger stride.

Introduce a mechanism to also allow upshifting register addresses.
Re-purpose reg_downshift into a more generic, signed reg_shift, whose
sign indicates the direction of the shift. To avoid confusion, also
introduce macros to explicitly indicate if we want to downshift or
upshift.

For bisectability, change any use of reg_downshift to use reg_shift.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Tested-by: Colin Foster <colin.foster@in-advantage.com>
Link: https://lore.kernel.org/r/20230407152604.105467-1-maxime.chevallier@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-07 17:28:19 +01:00
Konrad Dybcio
93f21d925f clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
Configure the disable wait value on the CX GDSC to ensure we don't get
any undefined behavior. This was omitted when first adding the driver.

Fixes: 8397e24278 ("clk: qcom: Add GPU clock controller driver for SM6375")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230329140135.2178957-1-konrad.dybcio@linaro.org
2023-04-07 09:27:02 -07:00
Abhinav Kumar
75eab749e7 arm64: dts: qcom: sc7280: remove hbr3 support on herobrine boards
There are some interop issues seen across a few DP monitors with
HBR3 and herobrine boards where the DP display stays blank with hbr3.
This is still under investigation but in preparation for supporting
higher resolutions, its better to disable HBR3 till the issues are
root-caused as there is really no guarantee which monitors will show
the issue and which would not.

This can be enabled back after successful validation across more DP
sinks.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230329233416.27152-1-quic_abhinavk@quicinc.com
2023-04-07 09:26:37 -07:00
Aaron Lewis
dfdeda67ea KVM: x86/pmu: Prevent the PMU from counting disallowed events
When counting "Instructions Retired" (0xc0) in a guest, KVM will
occasionally increment the PMU counter regardless of if that event is
being filtered. This is because some PMU events are incremented via
kvm_pmu_trigger_event(), which doesn't know about the event filter. Add
the event filter to kvm_pmu_trigger_event(), so events that are
disallowed do not increment their counters.

Fixes: 9cd803d496 ("KVM: x86: Update vPMCs when retiring instructions")
Signed-off-by: Aaron Lewis <aaronlewis@google.com>
Reviewed-by: Like Xu <likexu@tencent.com>
Link: https://lore.kernel.org/r/20230307141400.1486314-2-aaronlewis@google.com
[sean: prepend "pmc" to the new function]
Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-04-07 09:24:16 -07:00
Tom Rix
672029caa5
ASoC: mediatek: mt8186: set variable aud_pinctrl to static
smatch reports
sound/soc/mediatek/mt8186/mt8186-afe-gpio.c:14:16: warning: symbol
  'aud_pinctrl' was not declared. Should it be static?

This variable is only used in one file so should be static.

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20230407115553.1968111-1-trix@redhat.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-07 17:23:08 +01:00
Konrad Dybcio
996c32b745 clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
The vast majority of shared RCGs were not marked as such. Fix it.

Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230404224719.909746-1-konrad.dybcio@linaro.org
2023-04-07 09:18:24 -07:00
Tushar Nimkar
88704a0cd7 soc: qcom: rpmh-rsc: Support RSC v3 minor versions
RSC v3 register offsets are same for all minor versions of v3. Fix a
minor version check to pick correct offsets for all v3 minor versions.

Fixes: 40482e4f73 ("soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets")
Signed-off-by: Tushar Nimkar <quic_tnimkar@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406115732.9293-1-quic_tnimkar@quicinc.com
2023-04-07 09:17:46 -07:00
Like Xu
4fa5843d81 KVM: x86/pmu: Fix a typo in kvm_pmu_request_counter_reprogam()
Fix a "reprogam" => "reprogram" typo in kvm_pmu_request_counter_reprogam().

Fixes: 68fb4757e8 ("KVM: x86/pmu: Defer reprogram_counter() to kvm_pmu_handle_event()")
Signed-off-by: Like Xu <likexu@tencent.com>
Link: https://lore.kernel.org/r/20230310113349.31799-1-likexu@tencent.com
[sean: trim the changelog]
Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-04-07 09:07:41 -07:00
Ahmed Zaki
9c85b7fa12 iavf: remove active_cvlans and active_svlans bitmaps
The VLAN filters info is currently being held in a list and 2 bitmaps
(active_cvlans and active_svlans). We are experiencing some racing where
data is not in sync in the list and bitmaps. For example, the VLAN is
initially added to the list but only when the PF replies, it is added to
the bitmap. If a user adds many V2 VLANS before the PF responds:

    while [ $((i++)) ]
        ip l add l eth0 name eth0.$i type vlan id $i

we might end up with more VLAN list entries than the designated limit.
Also, The "ip link show" will show more links added than the PF limit.

On the other and, the bitmaps are only used to check the number of VLAN
filters and to re-enable the filters when the interface goes from DOWN to
UP.

This patch gets rid of the bitmaps and uses the list only. To do that,
the states of the VLAN filter are modified:
1 - IAVF_VLAN_REMOVE: the entry needs to be totally removed after informing
  the PF. This is the "ip link del eth0.$i" path.
2 - IAVF_VLAN_DISABLE: (new) the netdev went down. The filter needs to be
  removed from the PF and then marked INACTIVE.
3 - IAVF_VLAN_INACTIVE: (new) no PF filter exists, but the user did not
  delete the VLAN.

Fixes: 48ccc43ecf ("iavf: Add support VIRTCHNL_VF_OFFLOAD_VLAN_V2 during netdev config")
Signed-off-by: Ahmed Zaki <ahmed.zaki@intel.com>
Tested-by: Rafal Romanowski <rafal.romanowski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2023-04-07 08:49:50 -07:00
Ahmed Zaki
0c0da0e951 iavf: refactor VLAN filter states
The VLAN filter states are currently being saved as individual bits.
This is error prone as multiple bits might be mistakenly set.

Fix by replacing the bits with a single state enum. Also, add an
"ACTIVE" state for filters that are accepted by the PF.

Signed-off-by: Ahmed Zaki <ahmed.zaki@intel.com>
Tested-by: Rafal Romanowski <rafal.romanowski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2023-04-07 08:49:50 -07:00
Krzysztof Kozlowski
d8cc9415a4 hwmon: constify pointers to hwmon_channel_info
HWmon core receives an array of pointers to hwmon_channel_info and it
does not modify it, thus it can be array of const pointers for safety.
This allows drivers to make them also const.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2023-04-07 08:45:17 -07:00
Andrew Lunn
218669c662 ARM64: dts: marvell: cn9310: Add missing phy-mode
The DSA framework has got more picky about always having a phy-mode
for the CPU port. The SoC Ethernet is being configured to
10gbase-r. Set the switch phy-mode based on this. Additionally, the
SoC Ethernet is using in-band signalling to determine the link speed,
so add same parameter to the switch.

Additionally, the cpu label has never actually been used in the
binding, so remove it.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-04-07 17:41:05 +02:00
Andrew Lunn
0939de7d89 ARM: dts: armada: Add missing phy-mode and fixed links
The DSA framework has got more picky about always having a phy-mode
for the CPU port. The Armada Ethernet supports RGMII, SGMII,
1000base-x and 2500Base-X. Set the switch phy-mode based on how the
SoC Ethernet ports is been configured. For RGMII mode, have the switch
add the delays.

Additionally, the cpu label has never actually been used in the
binding, so remove it.

Lastly, add a fixed-link node indicating the expected speed/duplex of
the link to the SoC.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-04-07 17:28:24 +02:00
Andrew Lunn
e2e1bcb19b ARM: dts: orion5: Add missing phy-mode and fixed links
The DSA framework has got more picky about always having a phy-mode
for the CPU port. The Orion5x Ethernet is an RGMII port. Set the
switch to impose the RGMII delays.

Additionally, the cpu label has never actually been used in the
binding, so remove it.

Lastly, add a fixed-link node indicating the expected speed/duplex of
the link to the SoC.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-04-07 17:28:24 +02:00
Andrew Lunn
8aea8659a5 ARM: dts: kirkwood: Add missing phy-mode and fixed links
The DSA framework has got more picky about always having a phy-mode
for the CPU port. The Kirkwood Ethernet is an RGMII port. Set the
switch to impose the RGMII delays.

Additionally, the cpu label has never actually been used in the
binding, so remove it.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-04-07 17:28:24 +02:00
Enrico Mioso
6d5a6740f6 arm64: dts: marvell: add DTS for GL.iNet GL-MV1000
The GL-MV1000 (Brume) is a small form-factor gateway router.
It is based on the Marvell Armada 88F3720 SOC (1GHz), has 3 gigabit ethernet ports, 1 GB RAM, 16M SPI flash, 8GB eMMC and an uSD slot, as well as an USB 2.0 type A and an USB 3.0 type C port.

Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
CC: Pali <pali@kernel.org>
Reviewed-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-04-07 17:23:24 +02:00
Thomas Weißschuh
f326e72a6e firmware: turris-mox-rwtm: make kobj_type structure constant
Since commit ee6d3dd4ed ("driver core: make kobj_type constant.")
the driver core allows the usage of const struct kobj_type.

Take advantage of this to constify the structure definition to prevent
modification at runtime.

Signed-off-by: Thomas Weißschuh <linux@weissschuh.net>
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-04-07 17:17:00 +02:00
Krzysztof Kozlowski
4b6a412ee5 arm64: dts: marvell: align thermal node names with bindings
Bindings expect thermal node names to end with '-thermal':

  armada-8040-db.dtb: thermal-zones: 'ap-thermal-cpu0', ... do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-04-07 17:07:59 +02:00
Robert Marko
22a9554e54 arm64: dts: marvell: mochabin: enlarge PCI memory window
Armada 7040 uses a rather small 15MB memory window for every PCI adapter,
however this is not sufficient for Qualcomm QCA6390 802.11ax cards that
are shipped along with the OpenWrt WLAN model of MOCHAbin as ath11k
requires at least 16MB of memory.

So, similar to what MACCHIATOBin has been doing for years, lets move
to using the second PCIe 2 memory window and expand it to 128MB to
make it future proof.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-04-07 17:01:08 +02:00
Srinivas Pandruvada
4f59630a5e platform/x86: intel-uncore-freq: Add client processors
Make Intel uncore frequency driver support to client processor starting
from Alder Lake.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: https://lore.kernel.org/r/20230330145939.1022261-1-srinivas.pandruvada@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-04-07 15:27:33 +02:00
Uros Bizjak
f96fb2df3e x86/apic: Fix atomic update of offset in reserve_eilvt_offset()
The detection of atomic update failure in reserve_eilvt_offset() is
not correct. The value returned by atomic_cmpxchg() should be compared
to the old value from the location to be updated.

If these two are the same, then atomic update succeeded and
"eilvt_offsets[offset]" location is updated to "new" in an atomic way.

Otherwise, the atomic update failed and it should be retried with the
value from "eilvt_offsets[offset]" - exactly what atomic_try_cmpxchg()
does in a correct and more optimal way.

Fixes: a68c439b19 ("apic, x86: Check if EILVT APIC registers are available (AMD only)")
Signed-off-by: Uros Bizjak <ubizjak@gmail.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230227160917.107820-1-ubizjak@gmail.com
2023-04-07 14:34:24 +02:00
Li zeming
73d73f5ee7 PM: core: Remove unnecessary (void *) conversions
Assignments from pointer variables of type (void *) do not require
explicit type casts, so remove such type cases from the code in
drivers/base/power/main.c where applicable.

Signed-off-by: Li zeming <zeming@nfschina.com>
[ rjw: Subject and changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-07 13:27:13 +02:00
Viresh Kumar
a038895e25 cpufreq: drivers with target_index() must set freq_table
Since the cpufreq core directly uses freq_table, for cpufreq drivers
that set their target_index() callback, make it mandatory for them to
set the same.

Since this is set per policy and normally from policy->init(), do this
from cpufreq_table_validate_and_sort() which gets called right after
->init().

Reported-by: Yajun Deng <yajun.deng@linux.dev>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-07 13:21:58 +02:00
Javier Martinez Canillas
e3adc46da3
drm/vkms: Remove <drm/drm_simple_kms_helper.h> include
The driver doesn't use simple-KMS helpers to set a simple display pipeline
but only the drm_simple_encoder_init() function to initialize an encoder.

That helper is just a wrapper of drm_encoder_init(), but passing a struct
drm_encoder_funcs that sets the .destroy handler to drm_encoder_cleanup().

Since the <drm/drm_simple_kms_helper.h> header is only included for this
helper and because the connector is initialized with drm_connector_init()
as well, do the same for the encoder and drop the header include.

Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Maíra Canal <mcanal@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230406110235.3092055-3-javierm@redhat.com
2023-04-07 13:16:38 +02:00
Javier Martinez Canillas
ca0376ba19
drm/vkms: Drop vkms_connector_destroy() wrapper
This helper is just a wrapper that calls drm_connector_cleanup(), there's
no need to have another level of indirection.

Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Maíra Canal <mcanal@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230406110235.3092055-2-javierm@redhat.com
2023-04-07 13:10:40 +02:00
Balsam CHIHI
561538f770 thermal/drivers/mediatek/lvts_thermal: Add AP domain for mt8195
Add MT8195 AP Domain support to LVTS Driver.

Take the opportunity to update the comments to show calibration data
information related to the new domain.

[dlezcano]: Massaged a bit the changelog

Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com
2023-04-07 11:18:28 +02:00
Balsam CHIHI
05aaa7fdb0 dt-bindings: thermal: mediatek: Add AP domain to LVTS thermal controllers for mt8195
Add AP Domain to LVTS thermal controllers dt-binding definition for mt8195.

Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230307154524.118541-2-bchihi@baylibre.com
2023-04-07 11:18:28 +02:00
Ye Xingchen
46d6cbb820 thermal: amlogic: Use dev_err_probe()
Replace the open-code with dev_err_probe() to simplify the code.

Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/202303241020110014476@zte.com.cn
2023-04-07 11:18:28 +02:00
Chen-Yu Tsai
13f03bcd02 thermal/drivers/mediatek/lvts_thermal: Fix sensor 1 interrupt status bitmask
The binary representation for sensor 1 interrupt status was incorrectly
assembled, when compared to the full table given in the same comment
section. The conversion into hex was also incorrect, leading to
incorrect interrupt status bitmask for sensor 1. This would cause the
driver to incorrectly identify changes for sensor 1, when in fact it
was sensor 0, or a sensor access time out.

Fix the binary and hex representations in the comments, and the actual
bitmask macro.

Fixes: f5f633b182 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230328031017.1360976-1-wenst@chromium.org
2023-04-07 11:18:28 +02:00
Lukas Bulwahn
45cc9c4f76 MAINTAINERS: adjust entry in THERMAL/POWER_ALLOCATOR after header movement
Commit 32a7a02117 ("thermal/core: Relocate the traces definition in
thermal directory") moves include/trace/events/thermal_power_allocator.h to
drivers/thermal/thermal_trace_ipa.h, but misses to adjust the file
entry for the THERMAL/POWER_ALLOCATOR section.

Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a
broken reference.

Adjust this file entry in THERMAL/POWER_ALLOCATOR.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230328091737.6785-1-lukas.bulwahn@gmail.com
2023-04-07 11:18:28 +02:00
Rob Herring
e4fdcfb1a1 dt-bindings: thermal: Drop unneeded quotes
Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230327170233.4109156-1-robh@kernel.org
2023-04-07 11:18:28 +02:00
Zhang Rui
ded2d383b1 thermal/core: Remove thermal_bind_params structure
Remove struct thermal_bind_params because no one is using it for thermal
binding now.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230330104526.3196-1-rui.zhang@intel.com
2023-04-07 11:18:22 +02:00
Mikko Perttunen
cdd6076b0a thermal/drivers/tegra-bpmp: Handle offline zones
Thermal zones located in power domains may not be accessible when
the domain is powergated. In this situation, reading the temperature
will return -BPMP_EFAULT. When evaluating trips, BPMP will internally
use -256C as the temperature for offline zones.

For smooth operation, for offline zones, return -EAGAIN when reading
the temperature and allow registration of zones even if they are
offline during probe.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230330094904.2589428-1-cyndis@kapsi.fi
2023-04-07 10:31:33 +02:00
Ye Xingchen
fee5caec88 thermal/drivers/rockchip: use devm_reset_control_array_get_exclusive()
Switch devm_reset_control_array_get() to
devm_reset_control_array_get_exclusive().

Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/202303241108553006227@zte.com.cn
2023-04-07 10:31:33 +02:00
Sebastian Reichel
c3d2718ae6 dt-bindings: rockchip-thermal: Support the RK3588 SoC compatible
Add a new compatible for the thermal sensor device on RK3588 SoCs.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230308112253.15659-8-sebastian.reichel@collabora.com
2023-04-07 10:31:33 +02:00
Finley Xiao
45d7b3867a thermal/drivers/rockchip: Support RK3588 SoC in the thermal driver
The RK3588 SoC has seven temperature sensor ADC channels:

- Chip Center
- CPU Cluster 1 (Dual A76 "Big" Cores)
- CPU Cluster 2 (Dual A76 "Big" Cores)
- CPU Cluster 0 (Quad A55 "Little" Cores)
- Power Domain Center
- Graphics Processing Unit
- Neural Processing Unit

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
[rebase, squash fixes]
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230308112253.15659-7-sebastian.reichel@collabora.com
2023-04-07 10:31:33 +02:00
Sebastian Reichel
267f596585 thermal/drivers/rockchip: Support dynamic sized sensor array
Dynamically allocate the sensors array based on the amount
of platform sensors in preparation for rk3588 support, which
needs 7 sensors.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230308112253.15659-6-sebastian.reichel@collabora.com
2023-04-07 10:31:33 +02:00
Sebastian Reichel
f7cef1b743 thermal/drivers/rockchip: Simplify channel id logic
Replace the channel ID lookup table by a simple offset, since
the channel IDs are consecutive.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20230308112253.15659-5-sebastian.reichel@collabora.com
2023-04-07 10:31:33 +02:00
Sebastian Reichel
cb71c5f904 thermal/drivers/rockchip: Use dev_err_probe
Use dev_err_probe to simplify error printing in the driver's probe
routine.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230308112253.15659-4-sebastian.reichel@collabora.com
2023-04-07 10:31:32 +02:00