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Author SHA1 Message Date
Libo Chen
39afe5d6fc sched/fair: Fix inaccurate tally of ttwu_move_affine
There are scenarios where non-affine wakeups are incorrectly counted as
affine wakeups by schedstats.

When wake_affine_idle() returns prev_cpu which doesn't equal to
nr_cpumask_bits, it will slip through the check: target == nr_cpumask_bits
in wake_affine() and be counted as if target == this_cpu in schedstats.

Replace target == nr_cpumask_bits with target != this_cpu to make sure
affine wakeups are accurately tallied.

Fixes: 806486c377 (sched/fair: Do not migrate if the prev_cpu is idle)
Suggested-by: Daniel Jordan <daniel.m.jordan@oracle.com>
Signed-off-by: Libo Chen <libo.chen@oracle.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
Link: https://lore.kernel.org/r/20220810223313.386614-1-libo.chen@oracle.com
2023-04-05 09:58:48 +02:00
Kan Liang
24d3ae2f37 perf/core: Fix the same task check in perf_event_set_output
The same task check in perf_event_set_output has some potential issues
for some usages.

For the current perf code, there is a problem if using of
perf_event_open() to have multiple samples getting into the same mmap’d
memory when they are both attached to the same process.
https://lore.kernel.org/all/92645262-D319-4068-9C44-2409EF44888E@gmail.com/
Because the event->ctx is not ready when the perf_event_set_output() is
invoked in the perf_event_open().

Besides the above issue, before the commit bd27568117 ("perf: Rewrite
core context handling"), perf record can errors out when sampling with
a hardware event and a software event as below.
 $ perf record -e cycles,dummy --per-thread ls
 failed to mmap with 22 (Invalid argument)
That's because that prior to the commit a hardware event and a software
event are from different task context.

The problem should be a long time issue since commit c3f00c7027
("perk: Separate find_get_context() from event initialization").

The task struct is stored in the event->hw.target for each per-thread
event. It is a more reliable way to determine whether two events are
attached to the same task.

The event->hw.target was also introduced several years ago by the
commit 50f16a8bf9 ("perf: Remove type specific target pointers"). It
can not only be used to fix the issue with the current code, but also
back port to fix the issues with an older kernel.

Note: The event->hw.target was introduced later than commit
c3f00c7027. The patch may cannot be applied between the commit
c3f00c7027 and commit 50f16a8bf9. Anybody that wants to back-port
this at that period may have to find other solutions.

Fixes: c3f00c7027 ("perf: Separate find_get_context() from event initialization")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lkml.kernel.org/r/20230322202449.512091-1-kan.liang@linux.intel.com
2023-04-05 09:58:46 +02:00
Peter Zijlstra
b168098912 perf: Optimize perf_pmu_migrate_context()
Thomas reported that offlining CPUs spends a lot of time in
synchronize_rcu() as called from perf_pmu_migrate_context() even though
he's not actually using uncore events.

Turns out, the thing is unconditionally waiting for RCU, even if there's
no actual events to migrate.

Fixes: 0cda4c0231 ("perf: Introduce perf_pmu_migrate_context()")
Reported-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Paul E. McKenney <paulmck@kernel.org>
Link: https://lkml.kernel.org/r/20230403090858.GT4253@hirez.programming.kicks-ass.net
2023-04-05 09:58:46 +02:00
Krzysztof Kozlowski
e154a338e1 dt-bindings: soc: samsung: exynos-pmu: allow phys as child on Exynos3 and Exynos4
Just like on Exynos5250, Exynos5420 and Exynos5433 the MIPI phy is
actually part of the Power Management Unit system controller thus allow
it as PMU's child.

Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230207192851.549242-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-04-05 09:52:11 +02:00
Jiaxun Yang
de34007751 MIPS: generic: Enable all CPUs supported by virt board in Kconfig
Enable extra CPUs that may be supported by virt board, including
R4x00 (R4000 in QEMU), Cavium Octeon (Octeon68XX in QEMU), loongson2e,
loongson2f.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
03be534e1b MIPS: Add board config for virt board
Aligned with QEMU MIPS virt board.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
78073b8f1f MIPS: Octeon: Disable CVMSEG by default on other platforms
QEMU can't emulate CVMSEG on generic platform for now.

Just disable it by default.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
0c6ff92773 MIPS: Loongson: Don't select platform features with CPU
ARCH_HAS_PHYS_TO_DMA and GPIOLIB are all platform level features
they shouldn't be selected with CPU.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
194a835210 MIPS: Loongson: Move arch cflags to MIPS top level Makefile
Arch cflags should be independent to Platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
b6007ff809 MIPS: Octeon: Allow CVMSEG to be disabled
Don't include cvmseg states into thread_status when
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE is not defined or 0.

Fix compile for kernel without this feature.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
6e90049162 MIPS: c-octeon: Provide alternative SMP cache flush function
Currently c-octeon relies on octeon's own smp function to flush
I-Cache. However this function is not available on generic platform.

Just use smp_call_function_many on generic platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
f641519409 MIPS: cpu-features: Enable octeon_cache by cpu_type
cpu_has_octeon_cache was tied to 0 for generic cpu-features,
whith this generic kernel built for octeon CPU won't boot.

Just enable this flag by cpu_type. It won't hurt orther platforms
because compiler will eliminate the code path on other processors.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
918d779569 MIPS: Octeon: Opt-out 4k_cache feature
Octeon has a different cache interface with traditional R4K one,
just opt-out this flag for octeon to avoid run R4K cache initialization
code accidentally.

Also remove ISA level assumption for 4k cache.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:09 +02:00
Jiaxun Yang
e1aa1dfef6 MIPS: mips-cm: Check availability of config registers
Prevent reading unsupported config register during probing process.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:08 +02:00
Jiaxun Yang
aa45787c0d MIPS: smp-cps: Disable coherence setup for unsupported ISA
We don't know how to do coherence setup on ISA before MIPS
Release 1.

As CPS support only servers simulation purpose on those cores,
and simulators are always coherent, just disable initialization
code and provide user a warning in case coherence is not setup
properly.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:08 +02:00
Jiaxun Yang
393a759647 MIPS: Move declaration of bcache ops to cache.c
bcache is not tied to CPU's cache interface. Just move those
declaration to cache.c so it can be avaialble to CPU with all
cache types.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-04-05 09:45:08 +02:00
Jacek Lawrynowicz
0ec8671837 accel/ivpu: Fix S3 system suspend when not idle
Wait for VPU to be idle in ivpu_pm_suspend_cb() before powering off
the device, so jobs are not lost and TDRs are not triggered after
resume.

Fixes: 852be13f3b ("accel/ivpu: Add PM support")
Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230331113603.2802515-3-stanislaw.gruszka@linux.intel.com
2023-04-05 09:07:26 +02:00
Karol Wachowski
774e7cb503 accel/ivpu: Add dma fence to command buffers only
Currently job->done_fence is added to every BO handle within a job. If job
handle (command buffer) is shared between multiple submits, KMD will add
the fence in each of them. Then bo_wait_ioctl() executed on command buffer
will exit only when all jobs containing that handle are done.

This creates deadlock scenario for user mode driver in case when job handle
is added as dependency of another job, because bo_wait_ioctl() of first job
will wait until second job finishes, and second job can not finish before
first one.

Having fences added only to job buffer handle allows user space to execute
bo_wait_ioctl() on the job even if it's handle is submitted with other job.

Fixes: cd7272215c ("accel/ivpu: Add command buffer submission logic")
Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com>
Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230331113603.2802515-2-stanislaw.gruszka@linux.intel.com
2023-04-05 09:06:38 +02:00
Karol Wachowski
cb949ce504 accel/ivpu: Remove D3hot delay for Meteorlake
VPU on MTL has hardware optimizations and does not require 10ms
D0 - D3hot transition delay imposed by PCI specification (PCIe
r6.0, sec 5.9.) .

The delay removal is traditionally done by adding PCI ID to
quirk_remove_d3hot_delay() in drivers/pci/quirks.c . But since
we do not need that optimization before driver probe and we
can better specify in the ivpu driver on what (future) hardware
use the optimization, we do not use quirk_remove_d3hot_delay()
for that.

Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com>
Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230403121545.2995279-1-stanislaw.gruszka@linux.intel.com
2023-04-05 09:02:28 +02:00
Steev Klimaszewski
105560b4fc arm64: dts: qcom: sc8280xp-x13s: Add bluetooth
The Lenovo Thinkpad X13s has a WCN6855 Bluetooth controller on uart2,
add this.

Signed-off-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230326233812.28058-5-steev@kali.org
2023-04-04 20:51:38 -07:00
Bjorn Andersson
9db28f2975 arm64: dts: qcom: sc8280xp: Define uart2
Add the definition for uart2 for sc8280xp devices.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230326233812.28058-4-steev@kali.org
2023-04-04 20:51:37 -07:00
Manivannan Sadhasivam
de7d3d2f9d arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-19-manivannan.sadhasivam@linaro.org
2023-04-04 20:46:35 -07:00
Manivannan Sadhasivam
8921034240 arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-18-manivannan.sadhasivam@linaro.org
2023-04-04 20:46:20 -07:00
Manivannan Sadhasivam
b8e0ed06d1 arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-17-manivannan.sadhasivam@linaro.org
2023-04-04 20:46:20 -07:00
Bartosz Golaszewski
81767c1591 arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
Set line names for GPIO lines exposed by PMICs on sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
e5a893a7ce arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
Add GPIO controller nodes to PMICs that have the GPIO hooked up on
sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-15-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
fa40ca07e9 arm64: dts: qcom: sa8775p: pmic: add thermal zones
Add the thermal zones and associated alarm nodes for the PMICs that have
them hooked up on sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-12-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
cecff1f542 arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input
Add the RESIN input for sa8775p platforms' PMIC.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-11-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
b3a755ba16 arm64: dts: qcom: sa8775p: pmic: add the power key
Add the power key node under the PON node for PMIC #0 on sa8775p.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-10-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
d2d9a59274 arm64: dts: qcom: sa8775p: add the Power On device node
Add the PON node to PMIC #0 for sa8775p platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-9-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
634a3de323 arm64: dts: qcom: sa8775p: add support for the on-board PMICs
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced
to the SoC via SPMI. Enable the PMICs for sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-8-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
fdd55b3bab arm64: dts: qcom: sa8775p: add the spmi node
Add the SPMI PMIC Arbiter node for SA8775p platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-6-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
8696cd072e arm64: dts: qcom: sa8775p: add the pdc node
Add the Power Domain Controller node for SA8775p.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-5-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
f95f988cf7 arm64: dts: qcom: sa8775p: sort soc nodes by reg property
Sort all children of the soc node by the first address in their reg
property. This was mostly already the case but there were some nodes
that didn't follow it so fix it now for consistency.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-3-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
3fd7e2eec8 arm64: dts: qcom: sa8775p: pad reg properties to 8 digits
The file has inconsistent padding of the address part of soc node
children's reg properties. Fix it.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-2-brgl@bgdev.pl
2023-04-04 20:42:29 -07:00
Johan Hovold
ad8cd35c58 arm64: dts: qcom: sc8280xp-pmics: fix pon compatible and registers
The pmk8280 PMIC PON peripheral is gen3 and uses two sets of registers;
hlos and pbs.

This specifically fixes the following error message during boot when the
pbs registers are not defined:

	PON_PBS address missing, can't read HW debounce time

Note that this also enables the spurious interrupt workaround introduced
by commit 0b65118e6b ("Input: pm8941-pwrkey - add software key press
debouncing support") (which may or may not be needed).

Fixes: ccd3517faf ("arm64: dts: qcom: sc8280xp: Add reference device")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org> #Thinkpad X13s
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327122948.4323-1-johan+linaro@kernel.org
2023-04-04 20:37:45 -07:00
Krzysztof Kozlowski
894e258b6a arm64: dts: qcom: sc8280xp: correct Soundwire wakeup interrupt name
The bindings expect second Soundwire interrupt to be "wakeup" (Linux
driver takes by index):

  sc8280xp-crd.dtb: soundwire-controller@3330000: interrupt-names:1: 'wakeup' was expected

Fixes: c18773d162 ("arm64: dts: qcom: sc8280xp: add SoundWire and LPASS")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230403132328.61414-1-krzysztof.kozlowski@linaro.org
2023-04-04 20:35:26 -07:00
Konrad Dybcio
da51e2ceed arm64: dts: qcom: sdm845-tama: Enable GPI_DMA0/1
Enable both GPI DMAs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-6-2b1567c039d7@linaro.org
2023-04-04 20:29:45 -07:00
Konrad Dybcio
ff9108ea69 arm64: dts: qcom: sdm845-tama: Enable GPU
Enable the A630 GPU and its GMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-5-2b1567c039d7@linaro.org
2023-04-04 20:29:45 -07:00
Konrad Dybcio
39e0f8076f arm64: dts: qcom: sdm845-tama: Enable remoteprocs
Enable ADSP, CDSP and Venus.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-4-2b1567c039d7@linaro.org
2023-04-04 20:29:45 -07:00
Konrad Dybcio
1d99fee382 arm64: dts: qcom: sdm845-tama: Add regulator-system-load to l14a/l28a
Add the properties to ensure the ever so delicate touchscreen setup
matches downstream.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-3-2b1567c039d7@linaro.org
2023-04-04 20:29:45 -07:00
Konrad Dybcio
3ab8216de2 arm64: dts: qcom: sdm845-tama: Add Synaptics Touchscreen
Add required pins and RMI4 node to the common DT and remove it
from Akatsuki, as it uses a different touch.

Since the panels are super high tech proprietary incell, they
need to be handled with very precise timings. As such the panel
driver sets up the power rails and GPIOs and the touchscreen
driver *has to* probe afterwards.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-2-2b1567c039d7@linaro.org
2023-04-04 20:29:44 -07:00
Konrad Dybcio
5dcc6587fd arm64: dts: qcom: sdm845-tama: Add display nodes
Add required nodes to support display on XZ2/XZ2c. XZ3 has a
different power rail setup and needs to be handled separately.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-1-2b1567c039d7@linaro.org
2023-04-04 20:29:44 -07:00
Vinod Koul
c78ad8597e dt-bindings: firmware: document Qualcomm SC8180X SCM
Document the compatible for Qualcomm sc8180x SCM.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325122444.249507-2-vkoul@kernel.org
2023-04-04 20:23:56 -07:00
Adam Skladowski
26aae2310f arm64: dts: msm8953: Pad regs to 8 digits
Follow other dtses and pad regs to 8 digits.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-4-a39.skl@gmail.com
2023-04-04 20:23:15 -07:00
Adam Skladowski
c0494df2cd arm64: dts: msm8953: Drop unsupported dwc3 flag
Property phy_mode according to binding checker does not exist,
drop it.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-3-a39.skl@gmail.com
2023-04-04 20:23:15 -07:00
Adam Skladowski
635abd8775 arm64: dts: msm8953: Provide dsi_phy clocks to gcc
Provide clocks from dsi_phy to gcc, this will make
sure we don't fallback to global name lookup.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-2-a39.skl@gmail.com
2023-04-04 20:23:15 -07:00
Adam Skladowski
3042fb4b61 arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo
Assign RPM_SMD_XO_CLK_SRC from rpmcc in place
of fixed-clock where possible.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-1-a39.skl@gmail.com
2023-04-04 20:23:15 -07:00
Neil Armstrong
7b4c00e9cc arm64: defconfig: remove duplicate TYPEC_UCSI & QCOM_PMIC_GLINK
Both configs were already applied by 2 separate changes,
fix this to avoid:
arch/arm64/configs/defconfig:989:warning: override: reassigning to symbol TYPEC_UCSI
arch/arm64/configs/defconfig:1232:warning: override: reassigning to symbol QCOM_PMIC_GLINK

Fixes: 4ffd0b0019 ("arm64: defconfig: add PMIC GLINK modules")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324-topic-sm8450-upstream-defconfig-fixup-v1-1-2d75cc9b3c3d@linaro.org
2023-04-04 20:22:41 -07:00
Neil Armstrong
35fa9a7fc5 arm64: dts: qcom: sm8450: remove invalid properties in cluster-sleep nodes
Fixes the following DT bindings check error:
domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'
domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-2-0ca1bea1a843@linaro.org
2023-04-04 20:22:08 -07:00