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Author SHA1 Message Date
Matti Vaittinen
a9b7ce28fd regulator: bd96801: ROHM BD96801 PMIC regulators
The ROHM BD96801 "Scalable PMIC" is an automotive grade PMIC which can
scale to different applications by allowing chaining of PMICs. The PMIC
also supports various protection features which can be configured either
to fire IRQs - or to shut down power outputs when failure is detected.

The driver implements basic voltage control and sending error
notifications.

NOTE:
The driver does not support doing configuration which require the PMIC
to be in STBY state. The omitted feature set includes setting safety
limit values, changing LDO voltages and controlling enable state for
some regulators.
Also, the ERRB IRQ is not handled.

Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/50cf02b046df218a21a0f9c4820531d821fc20d4.1719473802.git.mazziesaccount@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:24:44 +01:00
Matti Vaittinen
7276f425b7 mfd: support ROHM BD96801 PMIC core
The ROHM BD96801 PMIC is highly customizable automotive grade PMIC
which integrates regulator and watchdog funtionalities.

Provide INTB IRQ and register accesses for regulator/watchdog drivers.

Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Link: https://lore.kernel.org/r/c5260e2dd222e3c64cdf410802bba195637ccb93.1719473802.git.mazziesaccount@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:24:44 +01:00
Matti Vaittinen
8b1a39362b dt-bindings: mfd: bd96801 PMIC core
ROHM BD96801 is a highly configurable automotive grade PMIC. Introduce
DT bindings for the BD96801 core.

Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/9fa3f30dede2b85871a89b20fe1eb13549418489.1719473802.git.mazziesaccount@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:24:44 +01:00
Matti Vaittinen
fd6e053d23 dt-bindings: ROHM BD96801 PMIC regulators
ROHM BD96801 is a highly configurable automotive grade PMIC. Introduce
DT bindings for the BD96801 regulators.

Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/53a05b77833cb3f06ecada906411c2f46eecea64.1719473802.git.mazziesaccount@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:24:44 +01:00
Bjørn Mork
2604e08ff2 USB: serial: option: add Fibocom FM350-GL
FM350-GL is 5G Sub-6 WWAN module which uses M.2 form factor interface.
It is based on Mediatek's MTK T700 CPU. The module supports PCIe Gen3
x1 and USB 2.0 and 3.0 interfaces.

The manufacturer states that USB is "for debug" but it has been
confirmed to be fully functional, except for modem-control requests on
some of the interfaces.

USB device composition is controlled by AT+GTUSBMODE=<mode> command.
Two values are currently supported for the <mode>:

40: RNDIS+AT+AP(GNSS)+META+DEBUG+NPT+ADB
41: RNDIS+AT+AP(GNSS)+META+DEBUG+NPT+ADB+AP(LOG)+AP(META) (default value)

[ Note that the functions above are not ordered by interface number. ]

Mode 40 corresponds to:

T:  Bus=03 Lev=02 Prnt=02 Port=00 Cnt=01 Dev#= 22 Spd=480  MxCh= 0
D:  Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=0e8d ProdID=7126 Rev= 0.01
S:  Manufacturer=Fibocom Wireless Inc.
S:  Product=FM350-GL
C:* #Ifs= 8 Cfg#= 1 Atr=a0 MxPwr=500mA
A:  FirstIf#= 0 IfCount= 2 Cls=e0(wlcon) Sub=01 Prot=03
I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=02 Prot=ff Driver=rndis_host
E:  Ad=82(I) Atr=03(Int.) MxPS=  64 Ivl=125us
I:* If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=rndis_host
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=(none)
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 7 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=07(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

Mode 41 corresponds to:

T:  Bus=03 Lev=02 Prnt=02 Port=00 Cnt=01 Dev#=  7 Spd=480  MxCh= 0
D:  Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=0e8d ProdID=7127 Rev= 0.01
S:  Manufacturer=Fibocom Wireless Inc.
S:  Product=FM350-GL
C:* #Ifs=10 Cfg#= 1 Atr=a0 MxPwr=500mA
A:  FirstIf#= 0 IfCount= 2 Cls=e0(wlcon) Sub=01 Prot=03
I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=02 Prot=ff Driver=rndis_host
E:  Ad=82(I) Atr=03(Int.) MxPS=  64 Ivl=125us
I:* If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=rndis_host
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=(none)
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 7 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=07(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 8 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=89(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=08(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 9 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=8a(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=09(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

Cc: stable@vger.kernel.org
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Johan Hovold <johan@kernel.org>
2024-06-27 10:21:46 +02:00
Krzysztof Kozlowski
174614d889 dt-bindings: soc: ti: am654-serdes-ctrl: Move to dedicated schema
ti,am654-serdes-ctrl is not a simple syscon device - it has children -
thus it should be fully documented in its own binding.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240626-dt-bindings-mfd-syscon-split-v3-5-3409903bb99b@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:16:36 +01:00
Krzysztof Kozlowski
430ed952ed dt-bindings: soc: microchip: sparx5-cpu-syscon: Move to dedicated schema
microchip,sparx5-cpu-syscon is not a simple syscon device - it has
children and implements simple-mfd compatible - thus it should be fully
documented in its own binding.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240626-dt-bindings-mfd-syscon-split-v3-4-3409903bb99b@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:15:47 +01:00
Krzysztof Kozlowski
c94ee67abd dt-bindings: soc: intel: lgm-syscon: Move to dedicated schema
intel,lgm-syscon is not a simple syscon device - it has children - thus
it should be fully documented in its own binding.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240626-dt-bindings-mfd-syscon-split-v3-3-3409903bb99b@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:14:42 +01:00
Krzysztof Kozlowski
cf87496ba2 dt-bindings: soc: sprd: sc9863a-glbregs: Document SC9863A syscon
Document sprd,sc9863a-glbregs compatible already used in DTS and other
bindings example.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240626-dt-bindings-mfd-syscon-split-v3-2-3409903bb99b@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:14:08 +01:00
Krzysztof Kozlowski
7661e68069 dt-bindings: mfd: syscon: Drop hwlocks
Apparently there is no in-tree DTS syscon node having hwlocks, so drop
the property to simplify the binding.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240626-dt-bindings-mfd-syscon-split-v3-1-3409903bb99b@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
2024-06-27 09:14:08 +01:00
Frank Wunderlich
df768350a8
arm64: dts: mt7622: fix switch probe on bananapi-r64
After commit 868ff5f494
("net: dsa: mt7530-mdio: read PHY address of switch from device tree")
the mt7531 switch on Bananapi-R64 was not detected.

mt7530-mdio mdio-bus:00: reset timeout
mt7530-mdio mdio-bus:00: probe with driver mt7530-mdio failed with error -110

Fix this by adding phy address in devicetree.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20240516204847.171029-1-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:26 +02:00
Chen-Yu Tsai
321ad586e6
arm64: dts: mediatek: Add MT8186 Voltorb Chromebooks
Add device trees for the MT8186 based Voltorb Chromebooks, also known
as the Acer Chromebook 311 (C723/C723T). The devices are clamshell
style laptops with an optional touchscreen.

The devices differ from the other existing MT8186 Chromebooks in that
it uses a higher speced / binned SoC which also requires a separate
PMIC for the big core cluster. Also, a different codec is used for
the internal speakers.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20240620094746.2404753-4-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:26 +02:00
Chen-Yu Tsai
9b4e414284
dt-bindings: arm: mediatek: Add MT8186 Voltorb Chromebooks
Add an entry for the MT8186 based Voltorb Chromebooks, also known as the
Acer Chromebook 311 (C723/C723T). The device is a clamshell style laptop
with an optional touchscreen.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240620094746.2404753-3-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:26 +02:00
AngeloGioacchino Del Regno
db77778a40
arm64: dts: mediatek: Makefile: Generate symbols for DTBO support
Add DTC_FLAGS '-@' for mt7986a-bananapi-bpi-r3 and -mini to
instruct the devicetree compiler to enable generation of symbols.

This allows proper support for Device Tree Overlay(s) for those
boards; future boards that need DTBO support are expected to add
their own DTC_FLAGS_{dtb-name}.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240620101830.1097548-1-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:26 +02:00
Chen-Yu Tsai
4055416e6c
arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add ports node for anx7625
The anx7625 binding requires a "ports" node as a container for the
"port" nodes. The jacuzzi dtsi file is missing it.

Add a "ports" node under the anx7625 node, and move the port related
nodes and properties under it.

Fixes: cabc71b08e ("arm64: dts: mt8183: Add kukui-jacuzzi-damu board")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240131083931.3970388-1-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:26 +02:00
Chen-Yu Tsai
70bf81dd2c
arm64: dts: mediatek: mt8183-pico6: Fix wake-on-X event node names
The wake-on-bt and wake-on-wlan nodes don't have a button- or event-
prefix that the gpio-keys binding requires.

Fix up the node names to satisfy the binding. While at it, also fix up
the GPIO overriding structure for the wake-on-wlan node. Instead of
referencing the gpio-keys node and then open coding the node, add a
label for the event node, and use that to reference and override the
GPIO settings.

Fixes: 055ef10ccd ("arm64: dts: mt8183: Add jacuzzi pico/pico6 board")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240131084043.3970576-1-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:26 +02:00
Pin-yen Lin
0b2f9d0e39
arm64: dts: mt8173: Add G2Touch touchscreen node
Lenovo Ideapad C330 Chromebook (MTK) uses G2Touch touchscreen as a
second source component.

Signed-off-by: Pin-yen Lin <treapking@chromium.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20231115043511.2670477-1-treapking@chromium.org
[Angelo: Rebased and added comment]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:25 +02:00
Hsin-Te Yuan
95173af725
arm64: dts: mediatek: mt8183-kukui: Fix the value of dlg,jack-det-rate mismatch
According to Documentation/devicetree/bindings/sound/dialog,da7219.yaml,
the value of `dlg,jack-det-rate` property should be "32_64" instead of
"32ms_64ms".

Fixes: dc0ff0fa3a ("ASoC: da7219: Add Jack insertion detection polarity")
Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org>
Link: https://lore.kernel.org/r/20240613-jack-rate-v2-1-ebc5f9f37931@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:25 +02:00
AngeloGioacchino Del Regno
c44589a890
arm64: dts: mediatek: mt8188: Add support for Mali GPU on Panfrost
Add the necessary OPP table for the GPU and also add a GPU node
to enable support for the Valhall-JM G57 MC3 found on this SoC,
using the Panfrost driver.

Link: https://lore.kernel.org/r/20240527093908.97574-6-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:25 +02:00
AngeloGioacchino Del Regno
eaf73e4224
arm64: dts: mediatek: mt8188: Add support for SoC power domains
In preparation for adding support for hardware IP that requires
power switching, add the necessary power domains nodes for the
MT8188 SoC.

Link: https://lore.kernel.org/r/20240527093908.97574-5-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:25 +02:00
AngeloGioacchino Del Regno
e15d0dd73e
arm64: dts: mediatek: mt8188: Add VDOSYS0/1 support for multimedia
Add support for the two VDOSYS blocks in MT8188, later on used for
various Multimedia related IP, including display and video codecs.

Link: https://lore.kernel.org/r/20240527093908.97574-4-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:25 +02:00
AngeloGioacchino Del Regno
45682a4fff
arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes
In preparation for adding multimedia nodes and power domains, add
support for the two Global Command Engine (GCE) mailboxes found in
this SoC.

Link: https://lore.kernel.org/r/20240527093908.97574-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:25 +02:00
Krzysztof Kozlowski
b220332f98
arm64: dts: mediatek: mt8173-elm: drop PMIC's syscon node
According to AngeloGioacchino Del Regno, the syscon node in PMIC is
neither needed nor used.  It looks like a solution to expose some of the
registers of PMIC.

Drop it to solve also incorrect number of entries in the "reg" property
and fix dtbs_check warning:

  mt8173-elm.dtb: syscon@c000: reg: [[0, 49152], [0, 264]] is too long

Link: https://lore.kernel.org/all/671a4b1e-3d95-438c-beae-d967e0ad1c77@collabora.com/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240612092421.52917-3-krzysztof.kozlowski@linaro.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:24 +02:00
Krzysztof Kozlowski
cc827572ad
arm64: dts: mediatek: mt8365: use a specific SCPSYS compatible
SoCs should use dedicated compatibles for each of their syscon nodes to
precisely describe the block.  Using an incorrect compatible does not
allow to properly match/validate children of the syscon device.  Replace
SYSCFG compatible, which does not have children, with a new dedicated
one for SCPSYS block.

Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240612092421.52917-2-krzysztof.kozlowski@linaro.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:24 +02:00
Krzysztof Kozlowski
1e8a1a9ea2
arm64: dts: mediatek: mt8365: drop incorrect power-domain-cells
The top SCPSYS node is not a power domain provider.  It's child
"power-controller" is instead.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240612092421.52917-1-krzysztof.kozlowski@linaro.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:24 +02:00
Rafał Miłecki
c3e87229b0
arm64: dts: mediatek: mt7981: add I2C controller
MT7981 has one on-SoC I2C controller that differs from recent Mediatek
blocks by having a different SLAVE_ADDR register offset (thus a custom
binding compatible string).

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240604063159.29216-1-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:24 +02:00
Rafał Miłecki
aebba1030a
arm64: dts: mediatek: mt7622: fix "emmc" pinctrl mux
Value "emmc_rst" is a group name and should be part of the "groups"
property.

This fixes:
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dtb: pinctrl@10211000: emmc-pins-default:mux:function: ['emmc', 'emmc_rst'] is too long
        from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dtb: pinctrl@10211000: emmc-pins-default:mux:function: ['emmc', 'emmc_rst'] is too long
        from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#

Fixes: 3725ba3f55 ("arm64: dts: mt7622: add pinctrl related device nodes")
Fixes: 0b6286dd96 ("arm64: dts: mt7622: add bananapi BPI-R64 board")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240604074916.7929-1-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:24 +02:00
Rafał Miłecki
660c230bf3
arm64: dts: mediatek: mt7988: add I2C controllers
MT7988 has three on-SoC I2C controllers that are the same hardware
blocks as already noticed on MT7981 chipsets.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240604064302.487-2-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:24 +02:00
Rafał Miłecki
09ff2216a0
arm64: dts: mediatek: mt7988: add PWM controller
MT7988 has on-SoC controller that can control up to 8 PWM interfaces.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240604064302.487-1-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:23 +02:00
Rafał Miłecki
95c465c439
arm64: dts: mediatek: Add OpenWrt One
OpenWrt One is the first ever OpenWrt product. It's based on MT7981B
(AKA Filogic 820) and has 1 GiB or DDR4 RAM. The rest of peripherals
remains to be added later.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240527115933.7396-4-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:23 +02:00
Rafał Miłecki
ff31b980c4
dt-bindings: arm64: dts: mediatek: Add OpenWrt One
OpenWrt One is the first ever OpenWrt product. It's based on MT7981B and
has entered an early production stage.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240527115933.7396-3-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:23 +02:00
Rafał Miłecki
1061f1b661
dt-bindings: vendor-prefixes: add OpenWrt
OpenWrt project (with the help of MediaTek and Banana Pi) has produced
its very first own hardware. It needs its own prefix.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240527115933.7396-2-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:23 +02:00
Frank Wunderlich
a098310bee
arm64: dts: mediatek: Add mt7986 based Bananapi R3 Mini
Add devicetree for Bananapi R3 Mini SBC.

Key features:
- MediaTek MT7986A(Filogic 830) Quad core ARM Cortex A53
- Wifi 6 2.4G/5G (MT7976C)
- 2G DDR RAM
- 8G eMMC flash
- 128MB Nand flash
- 2x 2.5GbE network port
- 1x M.2 Key B USB interface
- 1x M.2 KEY M PCIe interface
- 1x USB2.0 interface

source: https://wiki.banana-pi.org/Banana_Pi_BPI-R3_Mini

Co-developed-by: Eric Woudstra <ericwouds@gmail.com>
Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
Co-developed-by: Tianling Shen <cnsztl@gmail.com>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240510095707.6895-3-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:23 +02:00
Frank Wunderlich
4e293c219e
dt-bindings: arm64: mediatek: add BananaPi R3 Mini
Add MT7988A based BananaPi R3 Mini.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240510095707.6895-2-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:23 +02:00
Rafał Miłecki
454880d616
arm64: dts: mediatek: mt7981: add efuse block
MT7981 (Filogic 820) uses efuse for storing calibration data.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240514015154.11206-2-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:22 +02:00
Rafał Miłecki
f80cfe9616
arm64: dts: mediatek: mt7981: fix code alignment for PWM clocks
Align "clocks" array entries to start at the same column.

Fixes: cf29427573 ("arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240405105030.24559-1-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:22 +02:00
Geert Uytterhoeven
f14cdf03d1
arm64: dts: mediatek: mt7986a: bpi-r3: Convert to sugar syntax
Overlay syntactic sugar for generating target-path fragments is
supported by the version of dtc supplied with the kernel since commit
50aafd6089 ("scripts/dtc: Update to upstream version
v1.4.6-21-g84e414b0b5bc").  Hence convert the Bananapi R3 overlay
devicetree source files to sugar syntax, improving readability.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2fd900a30b5a0f7de4ea68f60bac250794b8cdb4.1716984213.git.geert+renesas@glider.be
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:22 +02:00
Pin-yen Lin
897a7edba9
arm64: dts: mediatek: mt8192-asurada: Add off-on-delay-us for pp3300_mipibrdg
Set off-on-delay-us to 500000 us for pp3300_mipibrdg to make sure it
complies with the panel's unprepare delay (the time to power down
completely) of the power sequence. Explicit configuration on the
regulator node is required because mt8192-asurada uses the same power
supply for the panel and the anx7625 DP bridge.

For example, the power sequence could be violated in this sequence:
1. Bridge on: panel goes off, but regulator doesn't turn off (refcount=1).
2. Bridge off: regulator turns off (refcount=0).
3. Bridge resume -> regulator turns on but the bridge driver doesn't
   check the delay.

Or in this sequence:
1. Bridge on: panel goes off. The regulator doesn't turn off (refcount=1),
   but the .unprepared_time in panel_edp is still updated.
2. Bridge off, regulator goes off (refcount=0).
3. Panel on, but the panel driver uses the wrong .unprepared_time to check
   the unprepare delay.

Fixes: f9f00b1f6b ("arm64: dts: mediatek: asurada: Add display regulators")
Signed-off-by: Pin-yen Lin <treapking@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240502154455.3427793-1-treapking@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:22 +02:00
Michael Walle
94aaf79a6a
arm64: dts: mediatek: add Kontron 3.5"-SBC-i1200
Add basic support for the Kontron 3.5" single board computer featuring a
Mediatek i1200 SoC (MT8395/MT8195).

Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240408080816.4134370-2-mwalle@kernel.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:22 +02:00
Michael Walle
1b4472430f
dt-bindings: arm64: mediatek: add Kontron 3.5"-SBC-i1200
Add the compatible string for the Kontron 3.5"-SBC-i1200 single board
computer.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240408080816.4134370-1-mwalle@kernel.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:22 +02:00
Macpaul Lin
666e6f39fa
arm64: dts: mediatek: mt8395-genio-1200-evk: add u3port1 for xhci1
This patch fixes an issue where xhci1 was not functioning properly because
the state and PHY settings were incorrect.

The introduction of the 'force-mode' property in the phy-mtk-tphy driver
allows for the correct initialization of xhci1 by updating the Device Tree
settings accordingly.

The necessary fixup which added support for the 'force-mode' switch in the
phy-mtk-tphy driver.
commit 9b27303003 ("phy: mediatek: tphy: add support force phy mode switch")
Link: https://lore.kernel.org/r/20231211025624.28991-2-chunfeng.yun@mediatek.com

Prior to this fix, the system would exhibit the following probe failure messages
for xhci1:
  xhci-mtk 11290000.usb: supply vbus not found, using dummy regulator
  xhci-mtk 11290000.usb: uwk - reg:0x400, version:104
  xhci-mtk 11290000.usb: xHCI Host Controller
  xhci-mtk 11290000.usb: new USB bus registered, assigned bus number 5
  xhci-mtk 11290000.usb: clocks are not stable (0x1003d0f)
  xhci-mtk 11290000.usb: can't setup: -110
  xhci-mtk 11290000.usb: USB bus 5 deregistered
  xhci-mtk: probe of 11290000.usb failed with error -110

With the application of this dts fixup, the aforementioned initialization errors
are resolved and xhci1 is working.

Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://lore.kernel.org/r/20240216095751.4937-1-macpaul.lin@mediatek.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:22 +02:00
AngeloGioacchino Del Regno
52b7afd5b9
arm64: mediatek: mt8195-cherry: Introduce the MT8195 Dojo Chromebook
Add a devicetree for the Cherry Dojo (HP Chromebook x360 13b-ca0002sa)
convertible type machine.

Differences with the already supported Tomato machines include:
 - Different speaker amplifiers (Dual MAX98380, one per channel)
 - I2C Touchscreen is on a different address (though still a HID device)
 - Has NVMe storage on the PCIe0 controller
 - Slightly different keyboard top row keymap

Link: https://lore.kernel.org/r/20240314103500.93158-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:21 +02:00
AngeloGioacchino Del Regno
a43bf5bebd
dt-bindings: arm: mediatek: Add MT8195 HP Chromebook x360 13b-ca0002sa
Add the MT8195 Cherry platform's Dojo machine, a convertible design
commercially known as the HP Chromebook x360 (13b-ca0002sa).

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240314103500.93158-2-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:21 +02:00
AngeloGioacchino Del Regno
458d92b55b
arm64: dts: mediatek: mt8186-corsola: Specify sound DAI links and routing
The drivers and bindings acquired support for specifying audio hardware
and links in device tree: describe and link the sound related HW of this
machine.

Link: https://lore.kernel.org/r/20240416071410.75620-19-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:21 +02:00
AngeloGioacchino Del Regno
87728e3ccf
arm64: dts: mediatek: mt8195-cherry: Specify sound DAI links and routing
The drivers and bindings acquired support for specifying audio hardware
and links in device tree: describe and link the sound related HW of this
machine.

Link: https://lore.kernel.org/r/20240416071410.75620-18-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:21 +02:00
Chen-Yu Tsai
27f0974a98
arm64: dts: mediatek: Drop mediatek,drive-strength-adv usage
The "mediatek,drive-strength-adv" pin config property has been
deprecated in favor of the generic "drive-strength-microamp" property.

Drop or convert all instances. A value of 0 disables the advanced
mode, which is the hardware default.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20240412075516.1199846-1-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:21 +02:00
Chen-Yu Tsai
e9a9055fdc
arm64: dts: mediatek: mt8183-kukui: Drop bogus output-enable property
The "output-enable" property is set on uart1's RTS pin. This is bogus
because the hardware does not actually have a controllable output
buffer. Secondly, the implementation incorrectly treats this property
as a request to switch the pin to GPIO output. This does not fit the
intended semantic of "output-enable" and it does not have any affect
either because the pin is muxed to the UART function, not the GPIO
function.

Drop the property.

Fixes: cd894e274b ("arm64: dts: mt8183: Add krane-sku176 board")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20240412075613.1200048-1-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:21 +02:00
AngeloGioacchino Del Regno
7ca7bbd289
arm64: dts: mediatek: mt8395-nio-12l: Add power supplies for CPU/GPU scaling
Add the necessary power supplies to safely enable CPU and GPU frequency
scaling.

Link: https://lore.kernel.org/r/20240409114211.310462-6-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:20 +02:00
AngeloGioacchino Del Regno
9af4238590
arm64: dts: mediatek: mt8395-nio-12l: Enable PHYs and USB role switch
Enable the PCIe0 PHY to be able to set calibrations read from eFuses,
improving the stability and performance of the PCIe link.

While at it, also enable the T-PHYs for both PCIe1 and for USB, allowing
the USB ports to finally switch to gadget mode if needed, and configure
the VBUS/ID pins of both USB ports for the same.

Link: https://lore.kernel.org/r/20240409114211.310462-5-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:20 +02:00
AngeloGioacchino Del Regno
048a70e314
arm64: dts: mediatek: mt8395-nio-12l: Define RSEL in microamperes
The paris pinctrl driver supports specifying the RSEL drive strength
in microamperes as well as internal bits definitions: choose to specify
those in uA to avoid using hardware specific values in device trees.

Link: https://lore.kernel.org/r/20240409114211.310462-4-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-06-27 10:10:20 +02:00