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Author SHA1 Message Date
Arnd Bergmann
34fdb46f0f This pull request contains Broadcom ARM/ARM64 SoC drivers updates for
6.1, please pull the following:
 
 - Guilherme adds a comment to the panic notifier, part of his big panic
 notifier rework series
 
 - William migrates all of ARCH_BCM4908 dependencies to ARCH_BCMBCA
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmMfeckACgkQh9CWnEQH
 BwQF9xAAr2z5G9EJkfWr13eTv6E1gvTXM96ljPt7yayVbmQeZOfR18Fl8orB+WtN
 YqkCIJ7eKRRevlPnrCLr4UghhFsHJABX1Oj8JdUtSJlQ5Gw5yqNGkJLipPSSQWoQ
 mxeOzyoZCXx6K7aiXeqQtV4OWGLmMJ/c7j6DDXpyqxY7vL4R5yURZRvi1/1lp9U2
 0kw9VPpmr51j0HdoM+esftKwR2lZdimYChCjp4MbBcMeMUWU4pDsOaxQmZCyl0w5
 F+OONd8YAUiyaxJVNgG/YQmJKKY8gZVriMo7tlt6U92jXxfPzuPFyj0Bnvb0GS8L
 h43uHcKCK7TRIkZknMPD+eNa0mOOkEbGTpO4uAwMCVQgKDCimaUQSk/shfe0jPo6
 4PWpkdOC8cpT7kfNr4erY/CVwzlsqb7L+2STnBQirJiAv+aR17g4zsp/CKHLe7GS
 2QEW7e75rb4RSeMv/bREAOkndndfMSWqkrXRiiLEy8dq7dp7V7mlFBNNejcomPj2
 O3COArbQUvpk+BTNs316PRm9PAJofYlgka1LysO527xOzKQEVG1O6GdaMRURvWnh
 MOoyzxd5lePvsudXjCsT7NXWwlwtByWmctTTbRr8jaMqL63OEOWymXOpt6FurNHI
 XcbumAh0LIMBiyAJpgpo0X9vbty0PLoFZSbtR6Jjmh2JmKXu2s8=
 =eiuT
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMjhVkACgkQmmx57+YA
 GNn4yw/+PQvLoXyeY3oM7deWLlqGx37yGTa8UE4MrNhi/v9Au0WsEZxUZ2j6w36E
 8GcwG4ZlmTy0Qhj6xY0TLt2M5mChO24VHd3yVunM9RCnmN1uXqxIGMX8xtEx6/KU
 Rl33x/KrJ9U1EgJpPCykIVFMoyq4Q9jER+RSgPlJasq64d2WXYcJVF78VJY9Dwk3
 a72x1+x3Wtz5LtkCLXjZD93XzkHnbwnoBF47hriRE4b+jrSAdhUm3ob2C7YTAJCH
 wXowBYm3ErM53o36u27/gRB60DhTUuo0/Pp41iK+H9RDMVhOVy/UZYTCY3N64wbr
 fTsjJ8BCEFoceIkANO2ymMIRpc03ki6uvq+x+UVJdAopSpkWo1Z38ooBDfDPk/ob
 yXZzoIVeS/jGHGF6nWd2UO/n+DVHSVdHhW/XuJflnEz0JxC+IPj2sGp1S/lIQnKN
 N1vhNhLqJMBO5pa4xcbLOXrGBp28UsYCgAM/SAdJyUh2zeifmqVRz+TKurZZCe1X
 5r2E9LSQgZ/henLXwqTAt3wyyLtuiIycLoHs9qFWL88UUX5nFHiLt18P/mdDKnOa
 3hB+jA+XDBMi6MUz4TpQqqsOFrLwFy5zWySHw33N8DDznsZzfEabwyTizfN832hX
 i1HGMgj2Iei9PLMJi2vJWRaP5DYl4Dw9HFoL2QHAWRYrdFg7Lo8=
 =7IUk
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-6.1/drivers' of https://github.com/Broadcom/stblinux into arm/drivers

This pull request contains Broadcom ARM/ARM64 SoC drivers updates for
6.1, please pull the following:

- Guilherme adds a comment to the panic notifier, part of his big panic
notifier rework series

- William migrates all of ARCH_BCM4908 dependencies to ARCH_BCMBCA

* tag 'arm-soc/for-6.1/drivers' of https://github.com/Broadcom/stblinux:
  arm64: bcmbca: Make BCM4908 drivers depend on ARCH_BCMBCA
  soc: bcm: brcmstb: Document panic notifier action and remove useless header

Link: https://lore.kernel.org/r/20220915023044.2350782-4-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15 22:04:41 +02:00
Arnd Bergmann
32c3d47fd7 This pull request contains Broadcom ARM64-based SoC changes for 6.1,
please pull the following:
 
 - Rafal adds the BCM4908 LED controller node and describes all 32 LED
 pins, he also adds support for the Asus GC-AC5300 LEDs
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmMfeXkACgkQh9CWnEQH
 BwS3XRAA1UyWHE6AqYSsLWcllNBxvbgJ9Fm5PqyY2+ZvMcHL3Pt5R0drY9tkQRfx
 ohiZmNoMxRgoVi79DGunVp9MWHtYzAyjoN8TOvS2er3zfEGBqoLTxPzNMDqcuX7y
 rtnFcrRAcr501gqqQ/ueaFxNDiIUY9aa48aPs7m7Tvqk9waKGtSDJ/y07+Bc/MYX
 RlsjKBkElfU8E/kcUQlGxGwEfaZ3V2nZtagf1En/BYtZ3X16T/zHJozu9TcI9YxQ
 yRxs7erW1GMOnrkVrlQFCH2TojhO6Ec5NtgSb2Ix9Bk80bU1l2hda6mm/lRFi81A
 AaJE1beJzspuQwHgS8zhKNwQNSzTptROkmzL5Ema7TKab72E9Oyp5cmTF5GaMskH
 BGunAghmi5SDU4Xz1sr5NnPSvnYwi/MdJvlPTSbzMGTuMk2Eze4vH5lAzsgePBr+
 Uw9B+nI/j6JIzQCrzzNZrr/M5i0PItuXvNO/ia8YbFnmQo4BvYwK4tE7G0i7kTmn
 YP428RYM7UontSBdEcJi/2P6JHoJvyxisbaMPgdBw8GP+qUgb8hiH/w9qJvIhcFX
 WfYZlILSKLbtnDob4o9HjN46W5IH5AbwcVy+Ax7qGA1l1yxxXjPB2CHJFtDCSpzK
 MfVoiUBqzdn/gZ68WQZbXuDchIBZG/FxFmr8zRyIiiQfWkHnHYY=
 =+IBl
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMjhSAACgkQmmx57+YA
 GNn7zw//ezQSo9ofE2JAQWzCs3d+3S3QAFqCz/PoBCmFS71Yoi59BoVD3ghVUdyB
 KZMEhWPgHa+MHJWHOqNM4TBbEF8J6MZNXIB/nrxG2L8h4QYmN995jlyQSsHX8yGd
 NEg9bwcTZ4lf5a2VZgzVgseNS3K4tOr0dGyIY68N1fmg4HaADbycYbOJjICxUDyL
 RNpghhJm3IIc/iwSS+kiY8Zny1MZnGj35xmvbzKOLek6DE6WeCZshP01MZD9BPJ2
 VAOQjHQ2z8XUjoHWEmkcl7HOnC6IILgdJwaRmrS8dHR1nIdN8n3J9ldpjdtCDXtD
 A+wjfhXsSg1O9yRfXfNnEXhPYma3lJMHllT266fas8344tXrrp2xmvIOI96UP+Um
 VhWsjkrTAXKBe26L5tkq5XEmgdmzclFPmn7gUzoGu7Ho5G2HvSZXTqng3OkGKlj/
 k6sIH+W56Ew0HfBkwwoZGiixp8YBepQG59jTDeOsosI4783k8Iwk8dZByxnlUH5o
 eHlSbmbbz5LpySMfanwbGSwoNUBmlG9n0OoNufzsQDNwsWPnl+iMH6JlyF/9qeDs
 yPDXZ3WAON7Mua6cFgeBDNyUOlw5uHZvfy1Lhx5MDwjsC05p+bd6At2dpjYHWTja
 t019ijZ1iD4eZqhF1Hd+tkFcI+xmOfIKeupQEG/vV5PEBktgEWk=
 =ybyG
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-6.1/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM64-based SoC changes for 6.1,
please pull the following:

- Rafal adds the BCM4908 LED controller node and describes all 32 LED
pins, he also adds support for the Asus GC-AC5300 LEDs

* tag 'arm-soc/for-6.1/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs
  arm64: dts: broadcom: bcm4908: add LEDs controller block
  arm64: dts: broadcom: bcm4908: add remaining LED pins

Link: https://lore.kernel.org/r/20220915023044.2350782-3-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15 22:03:43 +02:00
Arnd Bergmann
e33060879c This pull request contains Broadcom ARM-based SoC Device Tree updates
for 6.1, please pull the following:
 
 - Rafal improves the BCM5301X PCIe DT nodes schema validation by
 flagging the PCIe controller with a missing "device_type" property
 
 - William merges BCM4908 within BCMBCA since this chip is part of the
 Broadcom Broadband Carrier Access group and follows the architecture of
 those chips
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmMfeSQACgkQh9CWnEQH
 BwSu8A//bscpH0DKVVkZyji+UQN0c0WmBhPJTbedQRrMEABAmrF0kfJdGbNEe01r
 Qzb2GjhLpWDX5pL+SmDmjX0l9OQZiv83ruPCDK97HDqy1V1LbGBiT1I37R9eNW1v
 mWtL67RSEiuDKZdSfDEq/rkoPbYhowuYsSvIz53qr9EvFEjZXAXbRRpzKUJ/wDL1
 Nk/y+j6Vlc5ZzScsIZucRuIp9AJ4tH+Kaj+ZNcRs7cG01Ot4PtBa2gxCr7pmyiY4
 q9PFFWUZPQpKkMo/jLWvT4ajsHm7Fv4CLZK8h9GZOAuxYvmhqqLoPigDvBS3sug1
 Je2V2gdeuqiFgh9i6XHVM/XM2Hr+z8RHsFISjyHZQYUwSiWxo+E2p8pql/tMmh6Q
 swSX971xbbgBOVPC1JWuFTEtm8vWwGtlZXE5iptxWxTn5cq1pHNkg3wCNIMXjUei
 Bj78PM4ZyNPbJ5lq4RJP0ryT5N1UCYaX6sOh+nOD6GH1YXq+5XO4nx6/yeUEGKSM
 sGogAy40a0qP6UlHVdfayDgXFIfgSjY15Pfq5unSIEywQHhBR1GKDgrrAXSWQrux
 8F2kY0v2FDnAZeoYwWrJvrN24NmKm3TMeKjyoz7tu2KHYADWWQ1UrujFuXBAoIZC
 QeuFjfg/Ymar6A1BGwcQsrxDgMWruOLB9/029g8vLfoIuUYjNqA=
 =JcYR
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMjhE0ACgkQmmx57+YA
 GNmF5RAAoV7YjTJbbUqvuyJtqui491JY+ppMJtMYvq97PIIPhoNhQC2Yh3pfq/RG
 gL3a1+aXxMw5/YXOz2BJ5EIfHcfnkZF4DbIdGFviueMchh8sxTLivPHLcFRc7y6k
 RN9ydIpgq/XxrALGIq3N4zSl3D823HEbQ0UcN4RkxbPPqXDgTGxkwcvWrMaDJolb
 iLJpTaeael7VVaLNuPmDb0igEAAHbGNxQcu8MpRlaTwLZnJZHuOjxs8/h3ZhH+3g
 ZjDXw0qqO1kEdyqkJgUofJT8l0Hn54zoZDXZIJnhEiTsjcGR/X4jl2B+13vt8jW9
 MWcMh6DMK3U1zgRfAJnt4Ufas8iUc181yx3CRPBc/gIjh8t4arxD1wlepNcvPUBt
 AAM0Zi3j+CKzvLuU3IugOAWNLGUIcie6L/CWrEA2EYzd8IVtINd0mcWdPlP5L4/j
 4LwTJjQGNr+wedtWL1u90Oe3Qciax1IFwBRQBNR0y+4SRUhmzoVDKtFCiuRF/YpE
 GjmpLamdr+8XWjcGv3YvK50z6XTwSlWaMKyiHyDp3IGX4swmNJDHT3NyDhBL+ubH
 4jzBsBHJ2y/3PuaqruHUgD+r65kK88dVgfaSOZGNukdIdM8q2LobcZeXPB+nRdS2
 A67ekYdLcieeEFtkzaJOIogEpbou0CPgwxyStyDbWPZyk1JJkfA=
 =4L+j
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-6.1/devicetree' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM-based SoC Device Tree updates
for 6.1, please pull the following:

- Rafal improves the BCM5301X PCIe DT nodes schema validation by
flagging the PCIe controller with a missing "device_type" property

- William merges BCM4908 within BCMBCA since this chip is part of the
Broadcom Broadband Carrier Access group and follows the architecture of
those chips

* tag 'arm-soc/for-6.1/devicetree' of https://github.com/Broadcom/stblinux:
  arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA
  arm64: dts: Add BCM4908 generic board dts
  arm64: dts: Move BCM4908 dts to bcmbca folder
  arm64: dts: bcmbca: update BCM4908 board dts files
  dt-bindings: arm64: bcmbca: Update BCM4908 description
  dt-bindings: arm64: bcmbca: Merge BCM4908 into BCMBCA
  ARM: dts: BCM5301X: Add basic PCI controller properties

Link: https://lore.kernel.org/r/20220915023044.2350782-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15 22:00:13 +02:00
Arnd Bergmann
79774742bd This pull request contains Broadcom ARM64 defconfig changes for 6.1,
please pull the following:
 
 - William completes the removal of ARCH_BCM4908 by removing that Kconfig
 entry from the defconfig since it is being deleted after having been
 transitional through 6.0
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmMfeKAACgkQh9CWnEQH
 BwR65g/9HIe98J2cwiqIbkuCsXtRo5wODwax4pvxWxlaDR8NT3k++aWuxa2hhLKg
 2gzruTxcp4yN0oIpiiVW2hgTAAeaz6XdV9ct58egBXmf7xx2t5/a2B0jfaDKtNjj
 VyGio4nqYPHLxFTZg+zdt16Nd4iAfwExzeb8/kH2DkwTwkYtQxVfbjwfiYdmmcBu
 nXrQqCK2h7+yWhOvpXDcA9i5zagYGhEOBN2KmQfaf7cvhYxWI7ee+cSV1bW0dvXD
 3cm6Ijw+/be1UsuWkIK4aRpKfHdy9tUwsawYbqhQoyHxtj7P8tezq2mj79tyDE+l
 V2LpEjSeq91KxYhG49C3myVZzHdu/Unn9jPp+FOR8vkpSuM//AqCXXKkHWplu7/E
 1tJkOWJ2alM6T2cfXgatSxhoDweAxeA7NvhyYem69gIW58M88Av9e8nuxSIvMqc0
 TtshWnQvADcB0WOrQ/fzRJSG/pRVBW9IpsXa2+1WHkaHvwiDuG1cdQgv4EZJyZ2H
 z3I0fRod/0UC6yy56SxWgz9MPlaZy9wc0b6lV8gxckpf8hN4fdpWjSoZzgnuCuJZ
 +6vwJRgkkpwUptn41sz7X0W8Fz4dVk4WWaFq/8FSXqri51Gtxo2xCtuAZBeAqdFb
 HSYZBVkWM8g8rWpk+/9/wpnT8iAnF1MLyo+iTs65CA2V1g0QkaA=
 =Uw1u
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMjg8UACgkQmmx57+YA
 GNljkA/+MPtbdaVtvjbJ7PrfnsmqUrfONELLmP/mHiCHFOyOPqR44pEYNu4qjxtC
 76FZA6OqKuXZVBbZ0ojxq7n98jPO03RHCJ17pMdcrAGqVT4PXoCVkY0rPDnYgSEd
 4tuMnsTNqb9Pwx8qqKbvHsptyBKy1OVu8Na6hdKSFWErWI4y3j+n4e1Y4rboNIRS
 1WKf/FaRBgyFRP9obmGe6ixNpumrdDvmsLGgTF/IxlH3TfvvBOc2quSHwAiB4jA+
 lukpVUXUzqH4b/nIY+1/rJkalIfMAqdXW1Zvj7CisU8dOBLG7EoU6L6WIHVpH5Ot
 bSwZgt1KC8OvLkoOTrPEAmTS+HmRoKp1ie5fSSK4O1RLFG2nIe/UJIb5r1XIGguH
 6byzh45saTK/kotfWrahxgJw9y2u2Lka7UBh2ADmNuMEeonYREgIF9jT5fBycOo7
 KnEvswZkiJRutUhJ8B43LZcQxEsCCq9uID6mCJ8CiYmk/l+dQouhrU05znBEo0sf
 fvznajydRceOwcCwxOTM5So/vtdhAv6g+H+lt4ZU3d7hOsBR/6WOamoZCf9oxutU
 kU7gtdYgZahlCzjf5w7bM/Ac484C/wubvskSY7w0zjvijMf4TfS6fwlNY7tc7UeS
 Y+Ws2uWct7vmnQlStAiywgJ1wObtBvP0507v4+Fq8apavVF2byM=
 =DF0K
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-6.1/defconfig-arm64' of https://github.com/Broadcom/stblinux into arm/defconfig

This pull request contains Broadcom ARM64 defconfig changes for 6.1,
please pull the following:

- William completes the removal of ARCH_BCM4908 by removing that Kconfig
entry from the defconfig since it is being deleted after having been
transitional through 6.0

* tag 'arm-soc/for-6.1/defconfig-arm64' of https://github.com/Broadcom/stblinux:
  arm64: defconfig: remove BCM4908

Link: https://lore.kernel.org/r/20220915023044.2350782-1-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15 21:57:57 +02:00
Arnd Bergmann
aaa58141a5 AT91 fixes for 6.0 #2
It contains a fix for LAN966 SoCs that corrects the interrupt
 number for internal PHYs.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCYyLxGAAKCRCejrg/N2X7
 /Y3oAQDQ64mW15h0ZAgoHWpxVgIA2/h1RKvjphg7AgXhtsS1DgD/U94AFR3IlrTN
 BmDUUDutxXKXlJgIUy4zEdML4bMERQU=
 =DFFW
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMjgt8ACgkQmmx57+YA
 GNkCzA/7BL4dvTT4CBxf1/MgAhSxob+bl/libV+Kpr4lhpP+l70TzqYbilaerG6z
 ykIvPVlZWuOtv+78X1cmKTb1IAunjLjD/e5EYFzRUJpvsNr4m5xKWpka5LXD9a48
 VRt5alDWQaRKfP3vmnguKdmVbWvVje12GqyyUXz5KCtLhfSIeY+06QVs41Pkglwi
 tS55UKnOj6OLMn3Bz1Jz6CHPrGVAU6fM9yE5iJeqzBpjkP9pahaV/tqJYwhq2dQ/
 KZn95LYXGgQp5HwBgBgkEwtSPFJOmr85OculaMHFrFJ62jPeqd8oKc8J3+bM5B3d
 KzC/snet/UwvX8hthAFSZtYHZ0mJZFxPrkswjvn+9JHtO5XOm5buadgMRbiK8Ux/
 /j1c/WvSWoUUXskC3k4ZKUNIFMvahI7376VUoV7pPFe9fHW97mszWT8rzHXboCRw
 3FhKiMyqdcJWXlS0PMhb4XdqpcRJ3Cp2ngV15tOGfjZ+9BQXQw3lAyOxGcBI2ieX
 misITPW3tZ2+LKj6z3ehXPwTi99CfM8o5V/+1ySmoFONpXegKT2yF17qpiWBqV6B
 35I13Qm89RNsugX9udzFexoJ+1B9MipUjwmuBrKXuxVZ7Hw8qJ4OPi3Fv8bktea4
 0DE9UGj5qNyd6J4xqDKnzxuLhrRu17Z8l7+l5q92VRy1KfQSmqw=
 =HFlS
 -----END PGP SIGNATURE-----

Merge tag 'at91-fixes-6.0-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes

AT91 fixes for 6.0 #2

It contains a fix for LAN966 SoCs that corrects the interrupt
number for internal PHYs.

* tag 'at91-fixes-6.0-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: lan966x: Fix the interrupt number for internal PHYs

Link: https://lore.kernel.org/r/20220915105833.4159850-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15 21:54:07 +02:00
Akhil R
8e4428051d arm64: tegra: Add GPCDMA support for Tegra I2C
Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:38 +02:00
Mohan Kumar
af4c27738c arm64: tegra: Add iommus for HDA on Tegra234
Add the iommus property to the HDA node on Tegra234.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:38 +02:00
Mohan Kumar
0a4fa25042 arm64: tegra: Enable HDA node for Jetson AGX Orin
Enable HDA node for the Jetson AGX Orin platform.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:38 +02:00
Mikko Perttunen
b35f5b53a8 arm64: tegra: Add context isolation domains on Tegra234
Add Host1x context isolation domains on Tegra234. On Tegra234 we have
two IOMMUs that are connected to Host1x-channel programmed engines,
so we have to include domains for each of them.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:38 +02:00
Thierry Reding
b0c1a994f6 arm64: tegra: Fixup iommu-map property formatting
Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Diogo Ivo
a1e3de6ea5 arm64: dts: tegra: smaug: Add Wi-Fi node
The Google Pixel C contains a BRCM4354 Wi-Fi + BT module.
Add a DT node for its Wi-Fi functionality. Tested on Pixel C.

Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Diogo Ivo
a63c0cd837 arm64: dts: tegra: smaug: Add Bluetooth node
The Google Pixel C contains a BRCM4354 Wi-Fi + BT module.
Add a DT node for its BT functionality. Tested on Pixel C.

Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Thierry Reding
8aec2c17b9 arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit
A Multi-Gigabit Ethernet (MGBE) instance drives the primary Ethernet
port on the Jetson AGX Orin Developer Kit. Enable it.

Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Thierry Reding
610cdf3186 arm64: tegra: Add MGBE nodes on Tegra234
Add device tree nodes for the four instances of the Multi-Gigabit
Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs.

Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Thierry Reding
4f41e9d542 arm64: tegra: Fix up compatible for Tegra234 GPCDMA
There is no need to list the Tegra194-specific compatible for Tegra234
because the backwards-compatibility goes back all the way to Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Vidya Sagar
1d61cbb790 arm64: tegra: Enable PCIe slots in P3737-0000 board
Enable PCIe controller nodes to enable respective PCIe slots on
P3737-0000 board. Following is the ownership of slots by different
PCIe controllers.
Controller-1 : On-board Broadcom WiFi controller
Controller-4 : M.2 Key-M slot
Controller-5 : CEM form-factor x8 slot

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Vidya Sagar
ec142c44b0 arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances
grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us)
NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us)
respectively.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Vidya Sagar
cd42b26a52 arm64: tegra: Add regulators required for PCIe
Add regulator supplies required for PCIe functionality. The supplies
include 1.8V, 3.3V and 12V.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Thierry Reding
5b6b207ca5 Merge branch 'for-6.1/dt-bindings' into for-6.1/arm64/dt 2022-09-15 21:30:18 +02:00
Johan Hovold
677920072e arm64: dts: qcom: sm8450: fix UFS PHY serdes size
The size of the UFS PHY serdes register region is 0x1c4 and the
corresponding 'reg' property should specifically not include the
adjacent regions that are defined in the child node (e.g. tx and rx).

Fixes: 07fa917a33 ("arm64: dts: qcom: sm8450: add ufs nodes")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220915143431.19842-2-johan+linaro@kernel.org
2022-09-15 13:45:43 -05:00
Luca Weiss
5cbd20166f ARM: dts: qcom: apq8026-lg-lenok: Enable ADSP
Configure the reserved memory for ADSP and enable it.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220423155059.660387-5-luca@z3ntu.xyz
2022-09-15 13:44:42 -05:00
Luca Weiss
268c661c17 ARM: dts: qcom: apq8026-asus-sparrow: Enable ADSP
The customized reserved memory for ADSP is already configured, so we
just need to enable the node.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220423155059.660387-4-luca@z3ntu.xyz
2022-09-15 13:44:42 -05:00
Luca Weiss
25ba74dd60 ARM: dts: qcom: msm8226: Add ADSP node
Add a node for the adsp found on msm8226.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220423155059.660387-3-luca@z3ntu.xyz
2022-09-15 13:44:42 -05:00
Srinivas Pandruvada
97ec890d07 tools/power/x86/intel-speed-select: Release v1.13
Update version number.

This version includes fixes for:
- fix build failure when using gcc options -Wl,--as-needed
- Fix warning for perf_cap.cpu may be uninitialized
- Fix off by one check for MAX_DIE_PER_PACKAGE
- Fix issue with use of get_physical_die_id instead of
get_physical_die_id

Optimizations:
- Removed unused interfaces and functions
- Better handle package, die, cpu combination by
defining a struct and set at one place instead
at each user level.

New functional change:
- Warn if turbo is disabled and SST turbo-freq feature is requested

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:06 -07:00
Zhang Rui
921604b409 tools/power/x86/intel-speed-select: Optimize CPU initialization
Optimize CPU initialization.
Do cpu related initialization in one function, including setting the cpu
present_cpumask, target_cpumask, and cpu_map and core_count arrays.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:06 -07:00
Zhang Rui
ca56725d78 tools/power/x86/intel-speed-select: Utilize cpu_map to get physical id
cpu_map already has the cpu package id, die id information.
Thus there is no need to re-evaluating sysfs attributes or stored data
file to get the package id and die id of a given CPU each time.

In order to unitlize this, cpu_map needs to be created unconditionally.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:06 -07:00
Zhang Rui
a05b925ace tools/power/x86/intel-speed-select: Remove unused struct clos_config fields
pkg_id/die_id can be retrieved from struct isst_id, remove the redundant
clos_config->pkg_id/die_id fields.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:06 -07:00
Zhang Rui
3ba6a27566 tools/power/x86/intel-speed-select: Enforce isst_id value
Enforce the pkg/die value in struct isst_id are either -1 or a valid
value.

This helps avoid inconsistent or redundant checks.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Zhang Rui
e616059ee6 tools/power/x86/intel-speed-select: Do not export get_physical_id
Now, all the get_physical_pkg/die/core_id() users are inside
isst-config.c, so no need to export these APIs.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Zhang Rui
00bb07db5a tools/power/x86/intel-speed-select: Introduce is_cpu_in_power_domain helper
struct isst_id contains cpu, package and die info, and it can represent
a specific SST power domain.

Introduce is_cpu_in_power_domain() helper to identify if a cpu is in a
specified power_domain.

And cleanup the code to use the new helper.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Zhang Rui
56d6469291 tools/power/x86/intel-speed-select: Cleanup get_physical_id usage
struct isst_id already contains package and die id information, thus
there is no need to get the package and die id information, when struct
isst_id is already available.

Remove unneeded get_physical_package_id/get_physical_die_id usage.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Zhang Rui
30e0600e2f tools/power/x86/intel-speed-select: Convert more function to use isst_id
With pkg and die info added into struct isst_id, more functions can
be converted to use struct isst_id as parameter.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Zhang Rui
32d6ab4551 tools/power/x86/intel-speed-select: Add pkg and die in isst_id
Code uses pkg_id and die_id to refer to a specific power domain.

The pkg/die information is already settled at start time. Adding package
id and die id information into struct isst_id so that code does not need
to retrieve them at runtime.

More code cleanups can be done with the package/die info available.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Zhang Rui
850337ec7b tools/power/x86/intel-speed-select: Introduce struct isst_id
SST control is power-domain based rather than cpu based, on all the
systems including Sapphire Rapids and ealier.

SST core APIs uses cpu id as parameter, and use the underlying pkg_id and
die_id information to find a power domain, this is not straight forward
and introduces obscure logics in the code.

Introduce struct isst_id to represent a SST Power Domain.

All core APIs are converted to use struct isst_id as parameter instead of
using cpu id.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Zhang Rui
e278336912 tools/power/x86/intel-speed-select: Remove unused core_mask array
Remove unused core_mask array.

Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Zhang Rui
190ba96541 tools/power/x86/intel-speed-select: Remove dead code
Remove dead code.

Not functional change in this patch

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:16:05 -07:00
Hector Martin
68584e380e mailbox: apple: Implement poll_data() operation
This allows clients running in atomic context to poll for messages to
arrive.

Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-09-15 13:14:01 -05:00
Hector Martin
38ed8c888e mailbox: apple: Implement flush() operation
This allows clients to use the atomic-safe mailbox API style.

Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-09-15 13:14:01 -05:00
Zhang Rui
09db040339 tools/power/x86/intel-speed-select: Fix cpu count for TDP level display
In the function isst_ctdp_display_information(), call to the function
get_cpu_count() is using get_physical_die_id() instead of
get_physical_package_id(). This will result in wrong display of
CPU count in that level.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
[ Srinivas Pandruvada: fixed subject and change log ]
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-09-15 11:09:22 -07:00
Jens Axboe
fc7222c3a9 io_uring/msg_ring: check file type before putting
If we're invoked with a fixed file, follow the normal rules of not
calling io_fput_file(). Fixed files are permanently registered to the
ring, and do not need putting separately.

Cc: stable@vger.kernel.org
Fixes: aa184e8671 ("io_uring: don't attempt to IOPOLL for MSG_RING requests")
Signed-off-by: Jens Axboe <axboe@kernel.dk>
2022-09-15 11:44:35 -06:00
Maxime Ripard
433fb8a611 clk: tests: Add missing test case for ranges
Let's add a test on the rate range after a reparenting. This fails for
now, but it's worth having it to document the corner cases we don't
support yet.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-26-maxime@cerno.tech
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:34 -07:00
Maxime Ripard
af1e62f2ff clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d
The gfx3d clock is hand-crafting its own clk_rate_request in
clk_gfx3d_determine_rate to pass to the parent of that clock.

However, since the clk_rate_request is zero'd at creation, it will have
a max_rate of 0 which will break any code depending on the clock
boundaries.

That includes the recent commit 948fb0969e ("clk: Always clamp the
rounded rate") which will clamp the rate given to clk_round_rate() to
the current clock boundaries.

For the gfx3d clock, it means that since both the min_rate and max_rate
fields are set at zero, clk_round_rate() now always return 0.

Let's initialize the min_rate and max_rate fields properly for that
clock.

Fixes: 948fb0969e ("clk: Always clamp the rounded rate")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-25-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:29 -07:00
Maxime Ripard
2539932534 clk: Introduce the clk_hw_get_rate_range function
Some clock providers are hand-crafting their clk_rate_request, and need
to figure out the current boundaries of their clk_hw to fill it
properly.

Let's create such a function for clock providers.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-24-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:25 -07:00
Maxime Ripard
b46fd8dbe8 clk: Zero the clk_rate_request structure
In order to make sure we don't carry anything over from an already
existing clk_rate_request pointer we would pass to
clk_core_init_rate_req(), let's zero the entire structure before
initializing it.

Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-23-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:18 -07:00
Maxime Ripard
262ca38f4b clk: Stop forwarding clk_rate_requests to the parent
If the clock cannot modify its rate and has CLK_SET_RATE_PARENT,
clk_mux_determine_rate_flags(), clk_core_round_rate_nolock() and a
number of drivers will forward the clk_rate_request to the parent clock.

clk_core_round_rate_nolock() will pass the pointer directly, which means
that we pass a clk_rate_request to the parent that has the rate,
min_rate and max_rate of the child, and the best_parent_rate and
best_parent_hw fields will be relative to the child as well, so will
point to our current clock and its rate. The most common case for
CLK_SET_RATE_PARENT is that the child and parent clock rates will be
equal, so the rate field isn't a worry, but the other fields are.

Similarly, if the parent clock driver ever modifies the best_parent_rate
or best_parent_hw, this will be applied to the child once the call to
clk_core_round_rate_nolock() is done. best_parent_hw is probably not
going to be a valid parent, and best_parent_rate might lead to a parent
rate change different to the one that was initially computed.

clk_mux_determine_rate_flags() and the affected drivers will copy the
request before forwarding it to the parents, so they won't be affected
by the latter issue, but the former is still going to be there and will
lead to erroneous data and context being passed to the various clock
drivers in the same sub-tree.

Let's create two new functions, clk_core_forward_rate_req() and
clk_hw_forward_rate_request() for the framework and the clock providers
that will copy a request from a child clock and update the context to
match the parent's. We also update the relevant call sites in the
framework and drivers to use that new function.

Let's also add a test to make sure we avoid regressions there.

Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-22-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:11 -07:00
Maxime Ripard
22fb0e284f clk: Constify clk_has_parent()
clk_has_parent() doesn't modify the clocks being passed, so let's make
it const.

Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-21-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:06 -07:00
Maxime Ripard
1234a2c40b clk: Introduce clk_core_has_parent()
We will need to know if a clk_core pointer has a given parent in other
functions, so let's create a clk_core_has_parent() function that
clk_has_parent() will call into.

For good measure, let's add some unit tests as well to make sure it
works properly.

Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-20-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
[sboyd@kernel.org: Move tmp declaration, fix conditional to check for
current parent]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:31:58 -07:00
Maxime Ripard
666650b25a clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock
clk_mux_determine_rate_flags() will call into __clk_determine_rate()
with a clk_hw pointer, while it has access to the clk_core pointer
already.

This leads to back and forth between clk_hw and clk_core, while
__clk_determine_rate will only call clk_core_round_rate_nolock() with
the clk_core pointer it retrieved from the clk_hw.

Let's simplify things a bit by calling into clk_core_round_rate_nolock
directly.

Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-19-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:31:53 -07:00
Maxime Ripard
11c84a38fc clk: Add our request boundaries in clk_core_init_rate_req
The expectation is that a new clk_rate_request is initialized through a
call to clk_core_init_rate_req().

However, at the moment it only fills the parent rate and clk_hw pointer,
but omits the other fields such as the clock rate boundaries.

Some users of that function will update them after calling it, but most
don't.

As we are passed the clk_core pointer, we have access to those
boundaries in clk_core_init_rate_req() however, so let's just fill it
there and remove it from the few callers that do it right.

Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-18-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:31:49 -07:00
Maxime Ripard
c35e84b097 clk: Introduce clk_hw_init_rate_request()
clk-divider instantiates clk_rate_request internally for its round_rate
implementations to share the code with its determine_rate
implementations.

However, it's missing a few fields (min_rate, max_rate) that would be
initialized properly if it was using clk_core_init_rate_req().

Let's create the clk_hw_init_rate_request() function for clock providers
to be able to share the code to instation clk_rate_requests with the
framework. This will also be useful for some tests introduced in later
patches.

Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-17-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:31:40 -07:00