We really shouldn't allow a client to be created with cl_mach_cred set
unless it also has a principal name.
This also allows us to fail such cases immediately on EXCHANGE_ID as
opposed to waiting and incorrectly returning WRONG_CRED on the following
CREATE_SESSION.
Signed-off-by: J. Bruce Fields <bfields@redhat.com>
Technically the initialization in the NULL case isn't even needed as the
only caller already has target zeroed out, but it seems safer to keep
copy_cred generic.
Signed-off-by: J. Bruce Fields <bfields@redhat.com>
If we call __kvm_hyp_panic while a guest context is active, we call
__restore_sysregs before acquiring the system register values for the
panic, in the process throwing away the PAR_EL1 value at the point of
the panic.
This patch modifies __kvm_hyp_panic to stash the PAR_EL1 value prior to
restoring host register values, enabling us to report the original
values at the point of the panic.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Currently __kvm_hyp_panic uses %p for values which are not pointers,
such as the ESR value. This can confusingly lead to "(null)" being
printed for the value.
Use %x instead, and only use %p for host pointers.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
We were probing the physial distributor state for the active state of a
HW virtual IRQ, because we had seen evidence that the LR state was not
cleared when the guest deactivated a virtual interrupted.
However, this issue turned out to be a software bug in the GIC, which
was solved by: 84aab5e68c2a5e1e18d81ae8308c3ce25d501b29
(KVM: arm/arm64: arch_timer: Preserve physical dist. active
state on LR.active, 2015-11-24)
Therefore, get rid of the complexities and just look at the LR.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
We were incorrectly removing the active state from the physical
distributor on the timer interrupt when the timer output level was
deasserted. We shouldn't be doing this without considering the virtual
interrupt's active state, because the architecture requires that when an
LR has the HW bit set and the pending or active bits set, then the
physical interrupt must also have the corresponding bits set.
This addresses an issue where we have been observing an inconsistency
between the LR state and the physical distributor state where the LR
state was active and the physical distributor was not active, which
shouldn't happen.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
We were setting the physical active state on the GIC distributor in a
preemptible section, which could cause us to set the active state on
different physical CPU from the one we were actually going to run on,
hacoc ensues.
Since we are no longer descheduling/scheduling soft timers in the
flush/sync timer functions, simply moving the timer flush into a
non-preemptible section.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Commit 09605cc12c ("net ipv4: use preferred log methods") replaced
a few calls of pr_cont() after a console print without a trailing
newline by pr_info(), causing lines to be split during IP
autoconfiguration, like:
.
,
OK
IP-Config: Got DHCP answer from 192.168.97.254,
my address is 192.168.97.44
Convert these back to using pr_cont(), so it prints again:
., OK
IP-Config: Got DHCP answer from 192.168.97.254, my address is 192.168.97.44
Absorb the printing of "my address ..." into the previous call to
pr_info(), as there's no reason to use a continuation there.
Convert one more pr_info() to print nameservers while we're at it.
Fixes: 09605cc12c ("net ipv4: use preferred log methods")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: David S. Miller <davem@davemloft.net>
Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults
when a Stage 1 permission fault or device alignment fault should
have been reported.
This patch implements the workaround (which is to validate that the
Stage-1 translation actually succeeds) by using code patching.
Cc: stable@vger.kernel.org
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
When running a 32bit guest under a 64bit hypervisor, the ARMv8
architecture defines a mapping of the 32bit registers in the 64bit
space. This includes banked registers that are being demultiplexed
over the 64bit ones.
On exceptions caused by an operation involving a 32bit register, the
HW exposes the register number in the ESR_EL2 register. It was so
far understood that SW had to distinguish between AArch32 and AArch64
accesses (based on the current AArch32 mode and register number).
It turns out that I misinterpreted the ARM ARM, and the clue is in
D1.20.1: "For some exceptions, the exception syndrome given in the
ESR_ELx identifies one or more register numbers from the issued
instruction that generated the exception. Where the exception is
taken from an Exception level using AArch32 these register numbers
give the AArch64 view of the register."
Which means that the HW is already giving us the translated version,
and that we shouldn't try to interpret it at all (for example, doing
an MMIO operation from the IRQ mode using the LR register leads to
very unexpected behaviours).
The fix is thus not to perform a call to vcpu_reg32() at all from
vcpu_reg(), and use whatever register number is supplied directly.
The only case we need to find out about the mapping is when we
actively generate a register access, which only occurs when injecting
a fault in a guest.
Cc: stable@vger.kernel.org
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
The open coded tests for checking whether a PTE maps a page as
uncached use a flawed '(pte_val(xxx) & CONST) != CONST' pattern,
which is not guaranteed to work since the type of a mapping is
not a set of mutually exclusive bits
For HYP mappings, the type is an index into the MAIR table (i.e, the
index itself does not contain any information whatsoever about the
type of the mapping), and for stage-2 mappings it is a bit field where
normal memory and device types are defined as follows:
#define MT_S2_NORMAL 0xf
#define MT_S2_DEVICE_nGnRE 0x1
I.e., masking *and* comparing with the latter matches on the former,
and we have been getting lucky merely because the S2 device mappings
also have the PTE_UXN bit set, or we would misidentify memory mappings
as device mappings.
Since the unmap_range() code path (which contains one instance of the
flawed test) is used both for HYP mappings and stage-2 mappings, and
considering the difference between the two, it is non-trivial to fix
this by rewriting the tests in place, as it would involve passing
down the type of mapping through all the functions.
However, since HYP mappings and stage-2 mappings both deal with host
physical addresses, we can simply check whether the mapping is backed
by memory that is managed by the host kernel, and only perform the
D-cache maintenance if this is the case.
Cc: stable@vger.kernel.org
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Pavel Fedin <p.fedin@samsung.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
If the Renesas External IRQ Pin driver cannot find a functional clock,
it prints a warning, .e.g.
renesas_intc_irqpin fe78001c.interrupt-controller: unable to get clock
and continues, as the clock is optional, depending on the SoC type.
This warning may confuse users.
To fix this, add a flag to indicate that the clock is mandatory or
optional, and add a few more compatible entries:
- If the clock is mandatory (on R-Mobile A1 or SH-Mobile AG5), a
missing clock is now treated as a fatal error,
- If the clock is optional (on R-Car Gen1, or using the generic
"renesas,intc-irqpin" compatible value), the warning is no longer
printed.
This requires making struct intc_irqpin_irlm_config more generic by
renaming it to intc_irqpin_config, and adding a flag to indicate if IRLM
is needed.
The new clock flag is merged with the existing shared_irqs boolean into
a bitfield to save space.
Suggested-by: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lkml.kernel.org/r/1448377693-19597-1-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
intc_irqpin_priv.number_of_irqs is used inside intc_irqpin_probe() only,
so it can just become a local variable.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1448376581-9202-3-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since commit 4baadb9e05 ("ARM: shmobile: r8a7778: remove obsolete
setup code"), all Renesas SoCs with a renesas-intc-irqpin module are
only supported in generic DT-only ARM multi-platform builds. The driver
doesn't need to use platform data anymore, hence remove platform data
configuration.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1448376581-9202-2-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
building with $srctree != $objtree, perf-tar-* targets fail
to read the MANIFEST file and add the PERF-VERSION-FILE needed
by out-of-tree builds. The build errors and an incorrect tar is created:
$ make O=build-x86 perf-targz-src-pkg
TAR
cat: ../tools/perf/MANIFEST: No such file or directory
tar: perf-4.1.0-rc8/PERF-VERSION-FILE: Cannot stat: No such file or
dir..
tar: Exiting with failure status due to previous errors
Kbuild sets objtree to "." and srctree to ".." The command to output
MANIFEST becomes:
$(cd ..; echo $(cat ../tools/perf/MANIFEST))
Without MANIFEST, the entire kernel source tree is added to the perf
source tarball. The *correct* fix is to keep the cd and remove srctree
from cat command line since MANIFEST has wildcards that fail to expand
working directory isn't srctree.
Second, PERF-VERSION-FILE gets not added, because in-tree build path is
hardcoded to Makefile:
util/PERF-VERSION-GEN ../../$(perf-tar)/ 2>/dev/null)
The PERF-VERSION-GEN needs to be run from tools/perf directory,
and the output directory needs to be changed from relative to
to absolute. This can be achieved using the $(CURDIR) variable.
Also remove the error redirect to /dev/null which hid the error.
Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
Signed-off-by: Michal Marek <mmarek@suse.com>
After the introduction of the switch gpio reset API, I'm getting
build errors in configurations that disable CONFIG_GPIOLIB:
net/dsa/dsa.c:783:16: error: implicit declaration of function 'gpio_to_desc' [-Werror=implicit-function-declaration]
The reason is that linux/gpio/consumer.h is not automatically
included without gpiolib support. This adds an explicit #include
statement to make it compile in all configurations. The reset
functionality will not work without gpiolib, which is what you
get when disabling the feature.
As far as I can tell, gpiolib is supported on all architectures
on which you can have DSA at the moment.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: cc30c16344 ("net: dsa: Add support for a switch reset gpio")
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Coverity says:
*** CID 1338065: Error handling issues (CHECKED_RETURN)
/net/tipc/udp_media.c: 162 in tipc_udp_send_msg()
156 struct udp_media_addr *dst = (struct udp_media_addr *)&dest->value;
157 struct udp_media_addr *src = (struct udp_media_addr *)&b->addr.value;
158 struct sk_buff *clone;
159 struct rtable *rt;
160
161 if (skb_headroom(skb) < UDP_MIN_HEADROOM)
>>> CID 1338065: Error handling issues (CHECKED_RETURN)
>>> Calling "pskb_expand_head" without checking return value (as is done elsewhere 51 out of 56 times).
162 pskb_expand_head(skb, UDP_MIN_HEADROOM, 0, GFP_ATOMIC);
163
164 clone = skb_clone(skb, GFP_ATOMIC);
165 skb_set_inner_protocol(clone, htons(ETH_P_TIPC));
166 ub = rcu_dereference_rtnl(b->media_ptr);
167 if (!ub) {
When expanding buffer headroom over udp tunnel with pskb_expand_head(),
it's unfortunate that we don't check its return value. As a result, if
the function returns an error code due to the lack of memory, it may
cause unpredictable consequence as we unconditionally consider that
it's always successful.
Fixes: e53567948f ("tipc: conditionally expand buffer headroom over udp tunnel")
Reported-by: <scan-admin@coverity.com>
Cc: Stephen Hemminger <stephen@networkplumber.org>
Signed-off-by: Ying Xue <ying.xue@windriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The Jetson TX1 Development Kit is the successor of the Jetson TK1. The
Jetson TX1 is composed of the Jetson TX1 module (P2180) that connects to
the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel connected
via the P2597's display connector.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA P2597 I/O board is a carrier board for the Jetson TX1 module
and together they are also known as the Jetson TX1 Developer Kit. The
I/O board provides an RJ45 connector routed to the network adapter that
is part of the Jetson TX1 module. It exposes many other connectors such
as SATA, USB 3.0, HDMI, JTAG and PCIe, among others, as well. Dedicated
connectors allow display and camera modules to be attached. A full-size
SD slot is provided to extend storage beyond the 32 GiB of eMMC found
on the Jetson TX1 module.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC
with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials.
It is typically connected to some I/O board (such as the P2597) that has
the connectors needed to hook it up to the outside world.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA P2571 is an internal reference design that's very similar to
the P2371, but targetting different use-cases.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA P2371 is an internal reference design that uses a P2530
processor module hooked up to a P2595 I/O board and an optional display
module for a 1200x1920 MIPI DSI panel.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA P2595 I/O board is used in several reference designs and has
the connectors to connect the P2530 compute module to the outside world.
It features a USB 3.0 network adapter, a USB 3.0 port, an HDMI port, a
SATA port, an audio codec, a microSD card slot and a display connector,
among others.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA P2530 is a processor module used in several reference designs
that features a Tegra210 SoC, 4 GiB of LPDDR4 RAM, 16 GiB eMMC and other
essentials. It is typically connected to some I/O board that provides
the connectors needed to hook it up to the outside world.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired
with four Cortex-A53 cores in a switched configuration. It features a
GPU using the Maxwell architecture with support for DX11, SM4, OpenGL
4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware
accelerated en- and decoding of various video standards including
H.265, H.264 and VP8 at 4K resolutions and up to 60 fps.
Besides the multimedia features it also comes with a variety of I/O
controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.
Add a SoC-level device tree file that describes most of the hardware
available on the SoC. This includes only hardware for which a device
tree binding already exists or which is trivial to describe.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Norrin is a Tegra132-based FFD used as reference platform within NVIDIA.
Based on work by Allen Martin <amartin@nvidia.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
NVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124
but with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI
file for the SoC, which is mostly similar to the one for Tegra124.
Based on work by Allen Martin <amartin@nvidia.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
For historic reasons, the tegra platform selects USB_ULPI from architecture
code, but that hasn't really made sense for a long time, as the only
user of that code is the Tegra EHCI driver that has its own Kconfig
symbol.
This removes the 'select' statements from mach-tegra and drivers/soc/tegra
and adds them with the device driver that actually needs them.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra support several low-power (LPx) states, which are:
- LP0: CPU + Core voltage off and DRAM in self-refresh
- LP1: CPU voltage off and DRAM in self-refresh
- LP2: CPU voltage off
When entering any of the above states the tegra_disable_clean_inv_dcache()
function is called to flush the dcache. The function
tegra_disable_clean_inv_dcache() will either flush the entire data cache or
up to the Level of Unification Inner Shareable (LoUIS) depending on the
value in r0. When tegra_disable_clean_inv_dcache() is called by
tegra20_sleep_core_finish() or tegra30_sleep_core_finish(), to enter LP0
and LP1 power state, the r0 register contains a physical memory address
which will not be equal to TEGRA_FLUSH_CACHE_ALL (1) and so the data cache
will be only flushed to the LoUIS. However, when
tegra_disable_clean_inv_dcache() called by tegra_sleep_cpu_finish() to
enter to LP2 power state, r0 is set to TEGRA_FLUSH_CACHE_ALL to flush the
entire dcache.
Please note that tegra20_sleep_core_finish(), tegra30_sleep_core_finish()
and tegra_sleep_cpu_finish() are called by the boot CPU once all other CPUs
have been disabled and so it seems appropriate to flush the entire cache at
this stage.
Therefore, ensure that r0 is set to TEGRA_FLUSH_CACHE_ALL when calling
tegra_disable_clean_inv_dcache() from tegra20_sleep_core_finish() and
tegra30_sleep_core_finish().
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The symbol depends on ARCH_TEGRA and will default to y. There are no
circumstances under which it is desirable to disable this option.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired
with four Cortex-A53 cores in a switched configuration. It features a
GPU using the Maxwell architecture with support for DX11, SM4, OpenGL
4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware
accelerated en- and decoding of various video standards including
H.265, H.264 and VP8 at 4K resolutions and up to 60 fps.
Besides the multimedia features it also comes with a variety of I/O
controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.
Add a Kconfig option for Tegra210 to allow SoC-specific support to be
enabled for this new generation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Move per-SoC generation Kconfig symbols to drivers/soc/tegra/Kconfig to
gather them all in a single place. This directory is a natural location
for these options since it already contains the drivers that are shared
across 32-bit and 64-bit ARM architectures.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jeff Kirsher says:
====================
Intel Wired LAN Driver Updates 2015-11-23
This series contains updates to ixgbe, ixgbevf, fm10k, i40e and i40evf.
Jacob fixes an issue where VF could attempt to read queues it does not own,
so prevent this we check queue 0 before we continue.
Matthew fixes the MTU for jumbo frames for fm10k.
Julia Lawall cleans up a unneeded NULL test in ixgbe.
Mark cleans up a redundant header inclusion. Adds KR mode support for
CS4227 chip. Cleaned up diagnostic code, which is no longer needed, for
the CS4227 chip.
Jean Sacren fixes kernel documentation for ixgbe.
Alex Duyck fixes an fm10k and ixgbe issue in which the polling routine would
increase the budget for receive to at least 1 per queue if multiple queues were
present. This would result in receive packets being processed when the budget
was 0 which is meant to indicate that no receive can be handled. Also fixes
an ixgbevf performance issue where netperf test will starve for memory in the
time form one transmit interrupt to the next, so limit lowest interrupt rate
for adaptive interrupt moderation to 12K. Fixed up ixgbe and ixgbevf to
use napi_schedule_irqoff() where the drivers were run from hard interrupt
context or with interrupts already disabled in netpoll.
Jesse fixes a compiler warning about an unused variable for i40evf.
John Greene fixes an issue with ixgbevf, where if the VF driver is loaded
while the corresponding PH interface is down, the driver assigns a random
MAC address, can be overwritten with the value of hw->mac.perm_addr which
is 0 at that point. So avoid this case by initializing hw->mac.perm_addr
to the randomly generated address and do not set it unless we receive an
ACK from ixgbe.
Rasmus Villemoes cleans up some confusing code in i40e debugfs code.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Since commit c99cd90d98 ("ARM: shmobile: r8a7779: Remove legacy
SoC code"), R-Car SoCs are only supported in generic DT-only ARM
multi-platform builds. The driver doesn't need to match platform
devices by name anymore, hence remove the remaining platform_device_id
entries and platform device support.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Tejun Heo <tj@kernel.org>
Select CONFIG_DRM_DW_HDMI_AHB_AUDIO so that we have HDMI audio
supported by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The vf610 adc driver is present on Vybrid, MX6SX, MX6UL and MX7D.
Select it by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx_v6_v7_defconfig is not suitable for booting LS1021 as it needs
LPAE.
Remove this option.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch basically reverts the majority of patch 5407e24.
That patch eliminated the gfs2_qadata structure in favor of just
using the reservations structure. The problem with doing that is that
it increases the size of the reservations structure. That is not an
issue until it comes time to fold the reservations structure into the
inode in memory so we know it's always there. By separating out the
quota structure again, we aren't punishing the non-quota users by
making all the inodes bigger, requiring more slab space. This patch
creates a new slab area to allocate the quota stuff so it's managed
a little more sanely.
Signed-off-by: Bob Peterson <rpeterso@redhat.com>
The first commit of a buffer page updates the timestamp of that page. No
need to have the update to the next page add the timestamp too. It will only
be replaced by the first commit on that page anyway.
Only update to a page if it contains an event.
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
As cpu_buffer->tail_page may be modified by interrupts at almost any time,
the flow of logic is very important. Do not let gcc get smart with
re-reading cpu_buffer->tail_page by adding READ_ONCE() around most of its
accesses.
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Create a test to test instance creation and deletion. Several tasks are
created that create 3 directories and delete them. The tasks all create the
same directories. This places a stress on the code that creates and deletes
instances.
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Commit fcc742eaad "ring-buffer: Add event descriptor to simplify passing
data" added a descriptor that holds various data instead of passing around
several variables through parameters. The problem was that one of the
parameters was modified in a function and the code was designed not to have
an effect on that modified parameter. Now that the parameter is a
descriptor and any modifications to it are non-volatile, the size of the
data could be unnecessarily expanded.
Remove the extra space added if a timestamp was added and the event went
across the page.
Cc: stable@vger.kernel.org # 4.3+
Fixes: fcc742eaad "ring-buffer: Add event descriptor to simplify passing data"
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
On some machines the CRT connector may be fused off. The weird thing
about this setup is that the ADPA register works otherwise normally,
except the enable bit is hardwired to 0. No one knows of any fuse
register that would tell us if this is the case, so the only thing we
can do (apart from a blacklist) is to try and set the enable bit and see
if it sticks. If not, we don't register the connector at all. Obviously
if the bit is already set when loading the driver we can just assume it
works.
I've smoke tested this approach on several machines (GMCH and PCH),
some with actual CRT connectors, some with shadow connectors, and
obviously the machine (IVB) with the fused off connector. So far
I've not seen any ill effects from this probe.
The main benefit is that we can actually run igt on machines with
fused off connectors, without totally upsetting the state checker.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1448051741-22771-1-git-send-email-ville.syrjala@linux.intel.com
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
