Merge series from Richard Fitzgerald <rf@opensource.cirrus.com>:
The CAL_SET_STATUS and CAL_DATA_RB controls are volatile and read-only, but
the existing ASoC macros to define controls don't allow setting access
permissions, so those controls were marked as non-volatile read/write.
These four patches fix that.
The first two patches add two new control macros to soc.h. I really don't
like codec drivers open-coding a kcontrol_new content for a control that
will be managed by the ASoC info/get/put handlers. If a new type of ASoC
control definition is needed it's better to have it in soc.h so all the
dependencies between ASoC and the kcontrol_new content are in one place.
Merge series from Charles Keepax <ckeepax@opensource.cirrus.com>:
This series adds an initial SDCA class driver, this consists of a
primary driver attached to the SoundWire device, and auxiliary drivers
representing each of the functions of the SDCA device. These drivers all
use the APIs added over the past series's to provide the class
functionality, as such these final drivers themselves are quite thin.
Also a few fix ups at the start of the series that have gathered up
whilst the last SDCA series was in review.
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20251023204737.2716443-1-linus.walleij@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
AMD's SDCIAE (SDCI Allocation Enforcement) PQE feature enables system software
to control the portions of L3 cache used for direct insertion of data from I/O
devices into the L3 cache.
Introduce a generic resctrl cache resource property "io_alloc_capable" as the
first part of the new "io_alloc" resctrl feature that will support AMD's
SDCIAE. Any architecture can set a cache resource as "io_alloc_capable" if
a portion of the cache can be allocated for I/O traffic.
Set the "io_alloc_capable" property for the L3 cache resource on x86 (AMD)
systems that support SDCIAE.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/df85a9a6081674fd3ef6b4170920485512ce2ded.1762995456.git.babu.moger@amd.com
Add a kernel command-line parameter to enable or disable the exposure of
the L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) hardware
feature to resctrl.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/c623edf7cb369ba9da966de47d9f1b666778a40e.1762995456.git.babu.moger@amd.com
Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion
of data from I/O devices into the L3 cache. By directly caching data from I/O
devices rather than first storing the I/O data in DRAM, SDCI reduces demands on
DRAM bandwidth and reduces latency to the processor consuming the I/O data.
The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to
control the portion of the L3 cache used for SDCI.
When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache
partitions identified by the highest-supported L3_MASK_n register, where n is
the maximum supported CLOSID.
Add CPUID feature bit that can be used to configure SDCIAE.
The SDCIAE feature details are documented in:
AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
Injection Allocation Enforcement (SDCIAE).
available at https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/83ca10d981c48e86df2c3ad9658bb3ba3544c763.1762995456.git.babu.moger@amd.com
Currently, RAPL PMU support requires adding CPU model entries to
arch/x86/events/rapl.c for each new generation. However, RAPL MSRs are
not architectural and require platform-specific customization, making
arch/x86 an inappropriate location for this functionality.
The powercap subsystem already handles RAPL functionality and is the
natural place to consolidate all RAPL features. The powercap RAPL
driver already includes PMU support for TPMI-based RAPL interfaces,
making it straightforward to extend this support to MSR-based RAPL
interfaces as well.
This consolidation eliminates the need to maintain RAPL support in
multiple subsystems and provides a unified approach for both TPMI and
MSR-based RAPL implementations.
The MSR-based PMU support includes the following updates:
1. Register MSR-based PMU support for the supported platforms
and unregister it when no online CPUs remain in the package.
2. Remove existing checks that restrict RAPL PMU support to TPMI-based
interfaces and extend the logic to allow MSR-based RAPL interfaces.
3. Define a CPU model list to determine which processors should
register RAPL PMU interface through the powercap driver for
MSR-based RAPL, excluding those that support TPMI interface.
This list prevents conflicts with existing arch/x86 PMU code
that already registers RAPL PMU for some processors. Add
Panther Lake & Wildcat Lake to the CPU models list.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
[ rjw: Changelog edits ]
Link: https://patch.msgid.link/20251121000539.386069-3-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The current read_raw() implementation of the TPMI, MMIO and MSR
interfaces does not distinguish between atomic and non-atomic callers.
rapl_msr_read_raw() uses rdmsrq_safe_on_cpu(), which can sleep and
issue cross CPU calls. When MSR-based RAPL PMU support is enabled, PMU
event handlers can invoke this function from atomic context where
sleeping or rescheduling is not allowed. In atomic context, the caller
is already executing on the target CPU, so a direct rdmsrq() is
sufficient.
To support such usage, introduce an atomic flag to the read_raw()
interface to allow callers pass the context information. Modify the
common RAPL code to propagate this flag, and set the flag to reflect
the calling contexts.
Utilize the atomic flag in rapl_msr_read_raw() to perform direct MSR
read with rdmsrq() when running in atomic context, and a sanity check
to ensure target CPU matches the current CPU for such use cases.
The TPMI and MMIO implementations do not require special atomic
handling, so the flag is ignored in those paths.
This is a preparatory patch for adding MSR-based RAPL PMU support.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
[ rjw: Subject tweak ]
Link: https://patch.msgid.link/20251121000539.386069-2-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
driver, as well as the CEC extension to the DW-HDMI-QP driver.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmkZpqAQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgbqRCACrHGfhNyWP13LmjAHhClWMSC00oDDW7NAm
RYwDPAE/XHysIfEcHl+cnHK+kUCOtTmSqAUElCgML7g1Ix9LBkiNUdOYh7MVPyyK
AIZaXu2XH9YHIX9AzdgugyygHjFlvq9Uw4QnkSw50K35G5j+HcOFjwESlHvyqNHy
aCGhPaWj4yCHWcOD7mnKvh75QS33fhEnf+XAELB9aLS18rOQovXRZ1oGT0tlzfmC
kXbC8zFchqfb4zS4npZeS7A2kzZjqSu9JV7ZbXPzyvL0U7LjMh49hUVXrkU6icoQ
+jdNF/O8vICzsrvUkOCtwrSg04Ax95q68/pkWB9qRR5YOhwN1CUq
=LmM8
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzvsACgkQmmx57+YA
GNn0TRAAi5DjKimKa8J/zAFzYiRyp49z2vSZowQTBT8nzarnhMVm/ZqfSmzE+jmp
bl8EV4mrUYAiSedqnwzU8rEEwr0sFEcI5h1qri/aiRxrms5LWYsvcLpgwDk83fPo
l5LoQwN9IHa67LSXDwfEHRP4LLaJI/RK5KlZrgK5RITmaOs1Oc2N228PZIcHVROA
voYJ2Q44Y1BKvd86ABl0PK/fJppu0kr9whXWCqBVRXrI1n+fxUmr864aotCKm4W8
FDkImM4UTP5flaTCM3LNAwvPeymeJ5yD2m1VdwvdrGOeMntQMOic0yf5WrLO65sY
wi4825G3CSRxr+dlx1dl371urQ3IRmGgCQp8Ug70q0mim7LCMFEVQTL3A2RF8Jmq
iTNNwPX5J9/20m8Xr7nl4/Ktm3Ube96OzoQhjPwTpBJTIp+/mUDa1Qzdz2sprU3q
BLZGVzyufbU/OtBHJUb8KmnX8/vP7LbGhWuU79CwB4LdlgfjomWH4xngMxeew6Oq
We/bGc7bNCKZPrtaNG2wcYVQekLF0uKYQg9gePgQnyyyWTViBdB+fyStdKvzvbWF
vPHv5fCEO77hCoMv78obQVF3wiI9kB6/cqeOBIXCfbuqcIP0kH0ZeaZxxT0ZX+al
EUFeTxQh0SNGCfT/tE3nFl25SW1LRbsBdHgzB6MDXrl36/grcFc=
=qbBk
-----END PGP SIGNATURE-----
Merge tag 'v6.19-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/defconfig
Rockchip support for basic camera interface (CIF) and Synopsis DW-DP
driver, as well as the CEC extension to the DW-HDMI-QP driver.
* tag 'v6.19-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: defconfig: enable rockchip camera interface
arm64: defconfig: Enable DW HDMI QP CEC support
arm64: defconfig: Enable Rockchip extensions for Synopsys DW DP
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable config options for the hardare used across Fairphone 3, 4, and 5.
Then enable Novatek display panels founds on Xiaomi Pocophone F1, and
the SM8750 MTP, eUSB2 PHY found in SM8750, NSS clock controller found in
IPQ5424, the SX150x gpio expander used in QCS615 reference device, and
the support for UFS inline crypto.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmkbiyIACgkQCx85Pw2Z
rcW+sg//cHW1pWhtaAnLTn9jNPmNz3fgQfCIspLFyMiahf2bzN0aM+AxQMFpkjsQ
xZ/ZB6GF9dVMnqhcfF1KyB/y45lRaMaS6aQ87sl7s9SOoUkrRQ4vd8lPZrRofCjx
nvF1Fdkv6R2LsngwWPJqAtusOi1RD8nWNVhEgRc7EJjNLYI7qKbv3E+2Lk8ESjcs
5dgcFXmEOFxW7LD7NNFge0QTPzaHE9eRTLnm1lq5bOwqobsJrtE0hSIzMG0ZyfLU
h5c8zi9f+V/WOjcWMQ2klON9/hKOQHnHNVjH6vcXQKOD8PG/K5cG14ow2A/oLART
/fFjTxHrFVPKMW8AjQdYB5+IdKCm2wyfOn+/VyT03y513e47eWf3lrc+bJCpfAu1
Kp5YTnbqIq3WolzVE9eIASkRlt20EWxtLayD+G72Wms6V1eZfaCrKemxtfysOIEI
TmXwG6zc1PrcM71R+TzxbR5fkKU0ad1wFZbJObYWuTCxUV2xZv/8DUrSTGGEHhOI
GWiFAEzjN83xVjPqvU2pxwYZ0cIoMNVP5mbZpfZ45Tre7RRNGDIBIw+e57MoHBrR
t7dls0+8KoKFEVODdjnzpEmb+2VRk3e1yeBwIyyT15KGPnhU96OrMTE+90apT+XS
WEV//YKdDTyiQMg8ol51/Jm5QnraOpkZUBcoRWNVkzVbdPuXho0=
=Updz
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzsoACgkQmmx57+YA
GNkB3hAAhJgmXYkUIuDR0nLayyu2SeOdiRSJ4xKm8RGq8XwDjOYCXsdxTuPZmASj
lQWuEIZ1fHGhFfDfH4yMPLMKqb7MkatTxG96W0D3hXTZtCmsuV6m82l5T3/4drvA
6gy3Y6f8dC7fkrKRgZcQbuZ3S5gYhmzqSmgNIxSv0NRkVRXxSEJaexvk1gRMThyG
QZ7ME3CBzQlNn+/ZJq3n3SNOGp0NgPEaTUF57cY/mP0uqljg4fS82KdIVOCuVzGe
hlCSDNnxM9jCXU47YWlyq9qu3LYyB/vB3BBoBs/6DtP0bNtBfJwujkTu96/5AKEt
uOIW2cVfwKu9FjPXv+HxXrCMmk7z+HkfPMeLrNKsdo9jV5ESuKnjtoFJAUXeziP/
hvM2jJAdp52TdKH9qaKWGbMVZeMkb17nXQKi2F2hhMXTsvccySOAycClULCExEuq
TIOgNzk7JtuK1bbxnRQLXQDbhNzzneEhvrwuT7MbeTl8sac+gmXmjreOocT3Ka88
v/QBiNPTf7qqtW82zCMUNLRl7P+GvqfejWB7VGipf8re1s9wOSiuPQemPkvsOi3m
qiQHCFa2fhSCYDa6uQ/cd1Dx6jdlEm/TpCNIrBPpOtEc9XhCROoG0RSq2seY7nOh
JJ2xL9rYBtOyYdRdUaQyJdq82PPOK0nw8YWUg1hgjQzSTxi9+a0=
=3pxp
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-defconfig-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig
Qualcomm Arm64 defconfig updates for v6.19
Enable config options for the hardare used across Fairphone 3, 4, and 5.
Then enable Novatek display panels founds on Xiaomi Pocophone F1, and
the SM8750 MTP, eUSB2 PHY found in SM8750, NSS clock controller found in
IPQ5424, the SX150x gpio expander used in QCS615 reference device, and
the support for UFS inline crypto.
* tag 'qcom-arm64-defconfig-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: defconfig: Enable SX150x GPIO expander driver
arm64: defconfig: Build NSS clock controller driver for IPQ5424
arm64: defconfig: Enable SCSI UFS Crypto and Block Inline encryption drivers
arm64: defconfig: Add M31 eUSB2 PHY config
arm64: defconfig: Enable configs for Fairphone 3, 4, 5 smartphones
arm64: defconfig: Enable two Novatek display panels for MTP8750 and Tianma
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This update includes:
- CONFIG_MMC_SPI is set to module for at91_dt_defconfig
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCaRtHqAAKCRCejrg/N2X7
/SHYAQC7wLshtXYp+hl/yy3j9BRSoDCmpQLNP7IaOkXa/HyEpgD/VATNDNsXFsvc
ZbZH0oVbznx/q1by+5PuszyRmfgBbgM=
=jDaH
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgznMACgkQmmx57+YA
GNnPAA/+KqZvnvwA3xaSkwc0z4msi4VDj6+OkSLEqMTUtYYViEckrax87ZkvnOsv
EJZ0wvBvOHi3AGuBqOS8vQk6iQ79bfHYotQI6IGrNtKiSd0XJZcb+kQaXuhPXAt9
GR2BbZRizcc+C1YLlHCLiCVUsKJ9ileFQAb/893psVMY0x+Igk/7SjzzMpbp8UgU
zqUjaIFsWkLl60et+StNrs/q3getFNmPFXXCoA5ocG0GMfTPqy3l+w3xMoCKJnde
ydVgRPjY2U0PkqumuoGt2g3Z4sUm6UmUZYj1EwcR1fEzRQ23+ykXxBSQZDnFrrnW
1y1NabfyqxCRle1DFLb+8ypgPhRfM+bnVz2WM97FOVoAYsXce1/tn+W+Qmoxja8Q
jtvDkh8/Px0vSfpBZAuxbKCGNxEJyXCAJbfnF8mW1Vl+YmiAqQCt0qj6BTDUwy8L
mGz7X2ErqxPnhtDEyUTJgfPGMziRHr2Ga5qe+Cbxo6KBXeV009EkdwB/SZo0vnvt
8oOQu5Ag2DxREBAUoVOoBYibI6Mr/FQYw1gmEdqZp1OX9KD8GMvT5jC4sNunY8Ok
aWDGF3l1Ha0yJbrc8vUOvyF9zZaon5A/UFQ67Nk7aRGTDDrivJQQJnL7vCru5PI/
s6DV9RZfMrc4pwvgVWLz254Iktzdjc4M5Y6LYdb388dBqpnHRiM=
=W/Ld
-----END PGP SIGNATURE-----
Merge tag 'at91-defconfig-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/defconfig
Microchip AT91 defconfig updates for v6.19
This update includes:
- CONFIG_MMC_SPI is set to module for at91_dt_defconfig
* tag 'at91-defconfig-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: at91: at91_dt_defconfig: set MMC_SPI to module
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the new driver for the VRS PSEQ RTC found on Tegra234 and later.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmkYPmwACgkQ3SOs138+
s6FUZg//WetHNSGE42IAnDE97FEP5K3IpFIgfMnZLkU9JPXQK8Maf+N1NSeUctbe
MP9cJ9napK1O+tNS8w0XDzrHJWTof/goMlRxDW91I99qh9+OIUVBt7SLyqkvbZEw
OrAZNLbl1NwDs5/67jL2UHWrdjVnzxJ9zfu3BJbqjwfV3FRCMIpdwXyiNUKplV7z
yr79JFlvWO71q6Vkqf/UdapRzDelU0EuwMaAeQJljCKdsse/yCRULo6zcFDxEGu1
GXnZybGzbM4PEEp3BwoMxG7ytx/DFLShgIbOmvvVkOsWySwQlqy1Eo+5bSmPUWA4
MbOocxyHKJMpuYU/ehKJqDF6jbpO0+zA+Td43Hz37PYzv/m93WHd+ZviKb0Wluyd
03nna5JhTzANiLY6HAw3mtxCm4Fv1FT/kGtQ6V4ZBa+kGgKBXjnS76haLoTklhbk
BfGzVvDp657J9rO7evctm7IulSJM80xeomuAAp9At7GrUajILkG389bLS5NDyBhR
NBWp0+hUtMMdQLkM5gNYxBjxjHvtRLRJtE6S//6BxyH+L9vaxBDbYdUB+8hz1uRG
iIafKaI+TLrtaLnIjG5zwdr20JqCdaVMoiCLVPFzSWcAxjT2GtpzlM+EWaEGMWtk
WVLDgUyDpRbiGHYxXHP5SWh79pul8mrzN4FdC3/McH4hpFp/zgg=
=tHXb
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzaUACgkQmmx57+YA
GNlANRAAuBST65pnIAXhPbgaPslfIovsLcNnenlP8p7Gyqwjtjlhp7KoIlqQ1MAN
KIjwaBZWEzo8YObHBTGW/tCbq242yT6TBs1q09UrqKwM7h9xoYEhRzqhHmrCyrKS
f6PeoTO4Xn3aZGF9dquRE5RWOqT37P8+745fKVYf2VlJ2qo63koavT53j6/hvLep
vnyM4kFYjr5WMMqGwwpamnlTiBTsXNHG8j/K+4SIT73616biDHr2xpFjQwuwAMJW
i0CdVTmWU1oPXY5YXNvXvtkCqHc8T0oY2eHnr4w8cuBp6agL1ygAOkQguVt6Jkse
5U8Glaq4yQdVOOuAMWEJMs5RCvt+aZru6BEm9cdtQDHCtWngk+VI+PypJM4Kp8x4
n93y8GToy0qoivUOJ/VToIp24foT7ko/PCf/nDuPYTF+9CEWrUW19sA/lI/eb35H
f0n4BzNg4jXuvySW0kdN0Oo12JAeaxEbrRg2UlrLwXoRUFzMEZjdbBCdHxbZOYsB
czaMFgvSya/QpaguP2lcMTBKArXYuiIYO1K3yvvqV5CiM5EbiOXWt1/+04lDZzhB
cpEpkhmdfbjDaaP2MKrgi/t8XJsvBe47HyPV8R+v5jFdi5kaneQ+ThGajmBy2b1f
ZZXw2HJqkcR3CeGOYdIr+qoN5I+nWxUCErDGUCAwmUZa2gj4AKM=
=RMkG
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.19-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig
arm64: tegra: Default configuration changes for v6.19-rc1
Enable the new driver for the VRS PSEQ RTC found on Tegra234 and later.
* tag 'tegra-for-6.19-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Enable NVIDIA VRS PSEQ RTC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable ext4 by default on Tegra to restore systems booting from MMC.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmkYPHkACgkQ3SOs138+
s6EG7RAAwI1aJQEgDPLyHhOd5BVoUsxAvPqU8Kc+Futa5bnN33YKVmkj9PyElSjT
q+HPADbT4E/wBHkP6bDtdI2ySNZVYcLU80d1/2XjSZUvrIJ7umASX8bQqmRhNxZF
v9GNs2CfF5Fv+f8hI5fRfPYzBMaUk1Lj4HlAxl4bqHtkCS6q3QMP2QccdssegFGM
kiX+gv9xVOZmZ6Y7/mCdEZ6YJ4DKkxMFThCvFJZtP+NiRU9AIQY7zFTFvXsHgLEq
qhbk5tvoGi+edaH1vFEYK5wExb+cE4elxAHlZPDZWcrgAknnRE6gHVWzzuq97tgr
Bg+Ydp/LAWWfUk3naAz7SKJS2x2iuS6UYckRKN4r4icF7AtygM2hiap01WtbhLqq
O69my0ydkReVxyS4s6jgPPkwnoYL1D5ZLllNGripGZEkyF3SArq2EkF4I4NB5lzS
fH0m9nBcsxGCAavW2saXQclC2dlvMAUj8+xR68+lT6NR+E2wcTH52VzHg/IkUmIT
hwIa9Wo1ctU6To7m804Hb2TovNsOfKEYHCpO2n7wrwBb4X2egDZViI0742mzx2eX
mEOt4+4AdcdLOyGbaTZT0mSInCOG/OPIBioInpdlaFwUVKzYSnUgpWUjpyRi9AWj
Kk94QRGiRa41VBaxzPnfY6MlvaekuihKySx7exqzbNK7KqcMmXY=
=C4R/
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.19-arm-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig
ARM: tegra: Default configuration changes for v6.19-rc1
Enable ext4 by default on Tegra to restore systems booting from MMC.
* tag 'tegra-for-6.19-arm-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Enable EXT4 for Tegra
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
As MediaTek boards with UFS appeared some time ago, this adds a
single commit enabling the MediaTek UFS driver, allowing those
boards to boot over UFS as primary storage.
-----BEGIN PGP SIGNATURE-----
iLoEABYKAGIWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCaRMHjxsUgAAAAAAEAA5t
YW51MiwyLjUrMS4xMSwyLDIoHGFuZ2Vsb2dpb2FjY2hpbm8uZGVscmVnbm9AY29s
bGFib3JhLmNvbQAKCRCaNgTPrZeEeGzFAQC+GfbQfrl56jGrW02OCxNpjSzVwuTu
SYTlw5xwn9dwOQD9HPNqN8KPuCto81Rj/d7TZqzRhitLavhMYYBhS9GVhAY=
=0pZL
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzSMACgkQmmx57+YA
GNkPlQ/+K0fLkHkR4f6XvDyOXe4trgNFnG868jViY/4f4JfZCTCv8iScan2OT5w3
eDbVm/8YS7Uk5cRndWIiYibeR1DOGY0Ehm71Fmprl3n8if8JztWg5y0wENDeCE0e
BBDa5NiriyyQ7YTOiENY6AeeW5+9W3FRr/u9OuQ6BN+NHEPTml0AC+BdpVJxk0u+
oIYA+ccDoiqPn6U42vLiUzb2BCh+XLDaAXi7j+6WbIyCuJ1zvEpSbiwVYtKbhKLi
Qg6fgmMckLDon19EequoiABJSIwuoH+P7cOCBmb2/VGzV1680ovLvEqhZQPaOUoZ
ATWTLGCYRipkjBZfazIraYcUT4Ge8ZXhqB1N9t2DRh5zAq8xaWefylXu5OU3wowZ
r1RJ5kc/ysG9p5PC2kHPuf5Jmz4NTPM4CfUpzS38zUlRsPJU6hE8+No/tvnWttJ4
Tp0NJEBXqOJW58zN6B4XCrP7oStXLrZiic5ldMO+qG4ZXuLJplk1nDjVZOz2cava
JVs+ylWGUSycCzWpDs0xFXl9KVbtADTU8elTtpgN/uN+BchCtjkJEFex+CxnbPcU
RK/DeA3EBX1FYoJ76bEdNql9kT+LCb/w+54iPF3K9Zctp1E2TUCrI18EqXW6HAl3
m9uH+A7lNsFzVNvFTaAsGyHbcqG2EhCctsohd/Vf+5iz4jsix/U=
=d+Fg
-----END PGP SIGNATURE-----
Merge tag 'mtk-defconfig-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig
MediaTek defconfig updates
As MediaTek boards with UFS appeared some time ago, this adds a
single commit enabling the MediaTek UFS driver, allowing those
boards to boot over UFS as primary storage.
* tag 'mtk-defconfig-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: defconfig: Enable UFS support for MediaTek Genio 1200 EVK UFS board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the Exynos ACPM clocks driver. Samsung Exynos platforms
implement ACPM to provide support for clock configuration, PMIC
and temperature sensors.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20251010-acpm-clk-v6-5-321ee8826fd4@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251110121344.120785-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable support for the Renesas RZ/G3S and RZ/G3E thermal drivers,
and the RZ/T2H and RZ/N2H ADC drivers in the ARM64 defconfig,
- Refresh the ARM SH-Mobile defconfig for v6.18-rc1.
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaQSDwAAKCRCKwlD9ZEnx
cLmbAQDrw4g6TvLzEEuET5KvI9Bv/mKlSO3/dHc/Q8LRk3RWtAD6Ah3FatCWOXk8
ch65R/FOVxJbNkFsId8Pk2kk9CesYQw=
=XOpo
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzJ0ACgkQmmx57+YA
GNkLRxAAt9oq5X2IdPFSh86rmhWA+SaWrbjYUzrH0Bd9QZaOx9ZkOdqN5GQ+w5hc
giC5SbT2BYbI0w9SdCwOoETY9cvhWwd1AkIm4KLQcTWFiA6LwcMV/Im/rEjGGt8H
Mp906arN53eimFAaCbYABwwffd+FGN7npqyX0IepULdl7rn70MevOJIs1BAW8Ymz
wCTeRbZqBohtP774a82AOyqy1Wk6Lb9ERC+lGdqzb3lkdBLsovWJYYBVvO0gbk9U
0uCau7cQHpcLTFNpltyQvazyvKKkWIVOWzhKsVSzpP+9xOXvyBxYaeq/VfPe09r0
IxcI+856slNnFnp8oggfcauQmj9UmFFX8QbVXkd+GfR0HMAQcSgRW13MNO+cec0R
RkhwHM58rPYx+f1Z6ZSBMvmd84mIgds3bXOSiEfs1Y2Tcic1BcTxp9qzdraQb04d
AWk1xlglb00C92Fw7zg+3+6aZQ/3JVXYj6CZlRVEZY83RqkPLLUWIFKxVvXdJRwv
QCqDmmWz3Z2jW+fHMfhV2ilMyxcv/YT8q31ioy3xuQB5nVOhKT4fxoWkAzKL0Qf1
M02JlN3q6zPO0S/jS6rm6NW1/5862P0t9xQb8iw+Vj1P+TW84V8K3TXBfBZLZvZV
LjDBLPSrv2pzyZ0++M1PxSlyxuQf41GlQYR5iXDSxnLFVVcT3O4=
=l7pQ
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-defconfig-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig
Renesas ARM defconfig updates for v6.19
- Enable support for the Renesas RZ/G3S and RZ/G3E thermal drivers,
and the RZ/T2H and RZ/N2H ADC drivers in the ARM64 defconfig,
- Refresh the ARM SH-Mobile defconfig for v6.18-rc1.
* tag 'renesas-arm-defconfig-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: defconfig: Enable RZ/T2H / RZ/N2H ADC driver
ARM: shmobile: defconfig: Refresh for v6.18-rc1
arm64: defconfig: Enable the Renesas RZ/G3E thermal driver
arm64: defconfig: Enable Renesas RZ/G3S thermal driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The patch "7bd291abe2 sched: Unify the SCHED_{SMT,CLUSTER,MC} Kconfig"
has enabled the SCHED_MC/SCHED_SMT by default for arm64.
So remove the redundant code in defconfig.
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20251021075704.527626-1-shijie@os.amperecomputing.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add bindings for the serial and timer peripherals, and a basic soc dtsi
for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board
for this SoC. Add myself as maintainer for this platform for the time
being.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaR7j/AAKCRB4tDGHoIJi
0k3VAP9GQl/z1wt5KBj+Qhcvo84KW0gAUZVnHn1limK2EkB29wD+Ix8MTs3FWoRT
HghtdGPQZBnrOdsuJe3lDieDt2Oxtgg=
=ZLUq
-----END PGP SIGNATURE-----
Merge tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/newsoc
Initial Anlogic Platform Support
Add bindings for the serial and timer peripherals, and a basic soc dtsi
for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board
for this SoC. Add myself as maintainer for this platform for the time
being.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
MAINTAINERS: Setup support for Anlogic tree
riscv: defconfig: Enable Anlogic SoC
riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
riscv: dts: Add initial Anlogic DR1V90 SoC device tree
riscv: Add Anlogic SoC famly Kconfig support
dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
dt-bindings: riscv: Add Anlogic DR1V90
dt-bindings: riscv: Add Nuclei UX900 compatibles
dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
- initialize result before use in in error path
- fix uninitialized pointers with free attribute
-----BEGIN PGP SIGNATURE-----
iQJOBAABCgA4FiEE0qerISgy2SKkqO79Wr/6JGat8H4FAmka6uoaHGplbnMud2lr
bGFuZGVyQGxpbmFyby5vcmcACgkQWr/6JGat8H625hAAkeOfInc+UE3Y7KAuQ/o4
hbZE1wEQVJmCu1X7ugMowR7PWkntgOotUQPvGzgo8041UFpHCKSX+0y3yKud92yh
imiy7Gx9OxKYHUEC8J7SIuZpqJ2x87NPpLafA3+qLcYBAguY/aibpfhbDi9oi2qk
VZwisQuz5Gc5K2WJ5WUgj9Hxh9AlQQ6K8/oFl9QDZZv1H3GSYgiQJbVOJDVwjGir
4Ttm5b1NKMd8Jpa+sFkHOwQgOSvWujcUBRA+osopkz3JRRohgUrFQ+ShDc4/+ioe
NaQr6tJEiuBHihkSexPVyKRO7WyrIB/g33K5vB1GVwx/9MD8rWm/gU69jIMQn9PL
sNt6AMZx4A8MTL56slM9d9GYHQelFSS4alXgQW4C+iVzVcRMp0fiwDbxoe2Q7goy
MNX2Ic+ffYJJNkkBFye+udlmdH9Wqzz+NqIyb/9AEDx8TA1Fvl6sd19P+JedWH2q
dnbYVt4/N4l/8YJrh/T8/kJwvFheOC1Y5nlugf3wImcZgY3T9hhDOjYxMaCbZyCS
hcYzbylrMgzz2VP51xuClvI5OILKCA9fqR7nxVJo1a6fVTrT24jDELzE/hCkkPRS
Hra1yd/ZflIysuut7B8Yb2m0eSDhcyVtuf/kTFBndzduyxYq7Zza3J/UvrQUCHKy
0aACyNlFB4amfaRFfWHc21I=
=+IKZ
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgyywACgkQmmx57+YA
GNmIMw/9F1n6uAP0J0uVGLiDKSvxwN93oIYSoR3ToW/W4NUa67kJ/ScTO/ac+Mze
C2XAb4tY7rW3Ts34GWcW7G5sbV96HW8h81x9LsYGDdyNOzaLgESgvmsaObLH5RkY
K4DhgIyBTSpZf3QAqOd47BI2IkgHgcnjoyrCYMdC1b/wjrScwyvBxC7hbxS8Z4nu
mD2Cfdj/l41P09miemeLCXIcOHRJShtVRzZdszTmKqi3YEESAYSw57OKfE4flcuR
NhxLRwnZfetvuqW6wqNZBeoRLgTenpG5Qj2nPxJXpXG+gVw8EMvo87U/oq3bYNgu
+04EjN2Ulc3BPuupfq5K4x3Pmf0olkDJ/qyaeUc//R6ouwH/4hQvqRWUewhJ+1MF
wbfj/fPfOlhqPa5TiwwGWC9XK0ovq7bdcbEsVkJXJ7b4Do16zWa57dIS+heN4A/Z
UlXBvjEWgYd0H9+AGkWii3iFFy86FGRxflGYDfti6iRMeo3h+RbiNx3w8KbOgLg2
il6ne2TLvLg1pFqm67suPDXfyRRIKmkvIZtEyH8cdXmJ2zKYcrfoskd2Q9nd5bZE
Bzy0KrO18mXNTjcnd3ht+6hkYcAcQFetk6DgU7aKg0WDNOeWFPlnxr7BBASVSZjI
oiCcLW8GqCqJubMBjydso3q85AW8ig5phRCxuTP3kEbZPb71hMU=
=r+Hg
-----END PGP SIGNATURE-----
Merge tag 'qcomtee-fixes2-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into arm/fixes
QCOMTEE fixes2 for v6.18
- initialize result before use in in error path
- fix uninitialized pointers with free attribute
* tag 'qcomtee-fixes2-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee:
tee: qcomtee: initialize result before use in release worker
tee: qcomtee: fix uninitialized pointers with free attribute
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds support for the MT6582 SoC and its SMP bringup code.
This SoC is found in old smartphones and tablets from various
manufacturers.
-----BEGIN PGP SIGNATURE-----
iLoEABYKAGIWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCaRL8NhsUgAAAAAAEAA5t
YW51MiwyLjUrMS4xMSwyLDIoHGFuZ2Vsb2dpb2FjY2hpbm8uZGVscmVnbm9AY29s
bGFib3JhLmNvbQAKCRCaNgTPrZeEeBsMAQDfPwcnCdt+K1Fe/WD8Fj+tGzooGWsM
HbYg3GwqpgXdVAEA+Nt7IED9janSdcFSq2qEjbH66koY1qhVtdWw4L3U0Ag=
=UmLF
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgyXsACgkQmmx57+YA
GNmulg/+NxNWh4hL5mo6E2pY/wnEekxM4wvIim8BQd8T7ylUhV/JeRBe8j5c2sWx
+z40okgH7NrPIphvwTsarSEKCnzeeWyI+0ESw+XAqyttq5KXQCLLDfe8ZlK8Osg5
L/q+2XhfzL3iHqkDTgfTINdDvxllvPX+Bc7V1tcWloEfy0pSz1JCLyTQa1VOpEIT
SVo0A0m2rrtR59RPm5XbU6FyTXc2LNKHMWiwQuQpdJyUQOi0ep9H0DN0P5q5ri8P
HZq3OqdhJAMAGvQ8HRyYGvjagII46OTkivPqwssy30PzQoqLEktLVqyAoBcSn1Js
HPAznkboddfT0HSjuyVWd34WP/lgW+106kf0Aq3JHhE0k+wZCGMtgFl3r5349a//
X111DBJ7dAbeo3/4YqLtoFsEflZKD3YasIb3Dii9FnicynQqf5JMa6MTazyua6vY
8c5YjCiSZ0h67EzYINWXmZjcImxdl8YfKiFO914lyt8D7nv6jQFLw44mHlIiI0Io
bTumOIRa1wZ2qmvZXpR5M716fqyH8WctHk4Rk8oWhZSl20lJEIpu6gzGTTWHpOnY
zVtBiN9ZcY8/feREZtSlEWUbC4RfNEKqC6PphmLenxaDfxKkaOscAqmX8MDvjw0G
RduLbdsC4SunR9I+lwKRgQndczRrwBM9uAkbMtSun6/7v4/d1es=
=HHJi
-----END PGP SIGNATURE-----
Merge tag 'mtk-arm32-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/arm
MediaTek mach ARM32 updates
This adds support for the MT6582 SoC and its SMP bringup code.
This SoC is found in old smartphones and tablets from various
manufacturers.
* tag 'mtk-arm32-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
ARM: mediatek: add MT6582 smp bring up code
ARM: mediatek: add board_dt_compat entry for the MT6582 SoC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch series introduces platform support for Black Sesame Technologies
(BST) C1200 SoC and CDCU1.0 ADAS 4C2G board. BST is a leading automotive-grade
computing SoC provider focusing on intelligent driving, computer vision, and AI
capabilities for ADAS and autonomous driving applications. You can find more
information about the SoC and related boards at: https://bst.ai
This series provides the foundational platform enablement including device tree
bindings, SoC and board device trees, platform configuration, and maintainer
information. MMC/SDHCI driver support will be submitted in a separate patch series.
* bst/newsoc:
MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support
arm64: defconfig: enable BST platform support
arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board
arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs
dt-bindings: arm: add Black Sesame Technologies (bst) SoC
dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd.
Link: https://lore.kernel.org/all/20251016120558.2390960-1-yangzh0906@thundersoft.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add a MAINTAINERS entry for Black Sesame Technologies (BST) ARM SoC
support. This entry covers device tree bindings, drivers, and board files
for BST SoCs, and platform support.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable support for Black Sesame Technologies (BST) platform
in the ARM64 defconfig:
- CONFIG_ARCH_BST: Enable BST SoC platform support
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add device tree support for the Black Sesame Technologies (BST) C1200
CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC
family.
The changes include:
- Adding a new BST device tree directory
- Adding Makefile entries to build the BST platform device trees
- Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board
This board features a quad-core Cortex-A78 CPU, and various peripherals
including UART, and interrupt controller.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add ARCH_BST configuration option to enable support for Black Sesame
Technologies SoC family. BST produces automotive-grade system-on-chips
for intelligent driving, focusing on computer vision and AI capabilities.
The BST C1200 family includes SoCs for ADAS and autonomous driving
applications.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add device tree bindings for Black Sesame Technologies Arm SoC,
it consists several SoC models like C1200, etc.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Black Sesame Technologies Co., Ltd.s a leading automotive-grade
computing SoC and SoC-based intelligent vehicle solution provider.
Link: https://bst.ai/.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Late fixes and cleanups:
* Fix build warnings for unapplied overlays for PHYTEC, SA67 and certain TI EVM
* Fix pinmux of SD regulator control line on J721e SK
* Correct unit address of cbass_wakeup node for AM62L
-----BEGIN PGP SIGNATURE-----
iIYEABYIAC4WIQRQBrqaOmQ441h4YbUDQj8NV+8d1wUCaSAY7BAcdmlnbmVzaHJA
dGkuY29tAAoJEANCPw1X7x3XzpkBAPn1pdoqPU6YplG0Ajz8LnqlT/HOBFPBvk02
m5MgX9UsAP9n5d0ssAUkAFYoUDCNM2nvlzQtm+HuRS9RRrWrocWkCA==
=PSDa
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgxlQACgkQmmx57+YA
GNnXLQ//dum8Y+AvIe1WytZrQtaXvh5rhKakMMEpNvg8n0N+bW7/qUcPgj3g4e5P
QIhiJyp5jAoe+UmfhIMJz0DraP0q2fcpn34Rm3PuPfVS1EXjA6iR4rNA/z2iNE89
6hAch4aTuOMH6gnHmvzk5Fws8y8IA1HOGEUNU6TN70DNIh//KkcbOIkbRM+R0Iql
SgnuBnVGofacOU/0H99xBw0Djyu8egZvigQ9fdGh9JvFETBBVjgw07IfA9uxoDa/
a4+o3SFeIjb+oIt9f8DB2BJGePIsmEX0/NT8VYQhAndBHsjewH8+RmO6BFdb2SBL
iHDIrL5QCJHjQTDc/xOTO0j+NPcyvdGiFN343FpmLc09zf6NcJviPoKeLvPzP5AO
mn0ez0VhIZAlHfE5+UWI89yqGrbZ7oQxpsfdiwARta4rojhH56QBc1P3xrQCptHU
/mUKvpgAF/wRzjzpz7Gmb0nBuYPNX8SVtlsQfbyudPitbZKkK8DMk0/QnbaDUuCf
YeQlbr/9Y8VtdmIFtGCDj2k3d7QW030YsQgu8SzWtIYVgu5HARB1LKCuu32wrOFO
QZVlgSyx+XSLiksRV7xl5qab3ZQls5Bj/FRP6m+fUsmykExjfJ7w3El+Sj4e/l3n
6nS/RactuUoy1f+iqy+rNirmDCDKabMAJa7JQucolj5bvSawuCc=
=iXKo
-----END PGP SIGNATURE-----
Merge tag 'ti-k3-dt-for-v6.19-part2' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
TI K3 device tree updates for v6.19 part2
Late fixes and cleanups:
* Fix build warnings for unapplied overlays for PHYTEC, SA67 and certain TI EVM
* Fix pinmux of SD regulator control line on J721e SK
* Correct unit address of cbass_wakeup node for AM62L
* tag 'ti-k3-dt-for-v6.19-part2' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
arm64: dts: ti: k3-am62l: Fix unit address of cbass_wakeup
arm64: dts: ti: k3-j721e-sk: Fix pinmux for pin Y1 used by power regulator
arm64: dts: ti: Add missing applied DT overlay targets
arm64: dts: ti: sa67: add build time dtb for overlays
arm64: dts: ti: Enable build testing of PHYTEC board overlays
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Sophgo:
For CV18xx serials:
Add top syscon device related DTS change, the top system
controller provides register access to configure some
misc modules, such as usb2 phy and a dma multiplexer.
For SG2042:
There are two changes. The first one is to add DTS
definition for PCIe controllers for SoC SG2042 and
boards such as Pioneerbox/EVB_V1/EVB_V2 uses SG2042.
The second one is to add DTS to support SPI-NOR flash
controllers for this SoC and the same for related boards.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQTYPcWJ6By3aFu8IuKHG95Quc97dgUCaR1vJAAKCRCHG95Quc97
dm3BAP9eP96c/3Irv4be9+WmINoNDXXxfoVxH5OVpqLbDge23AEA+KfP3pHOTWrU
keb2z7sjWek0QoDatdPL5HQojQ1IRQ0=
=Iio2
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgxd0ACgkQmmx57+YA
GNntoRAAs4ms5xkTrGuhAc60jReKxL69NFaYPLH25ia82yIVlph9hqOyiDK1vLpj
mIsz/cbl6N8HU6u7IuhoWtUzrHA6FtbUgt+0y2C9Sj5lEA2sSEuqMXvlTd4njLhO
4U/ICxl8w4SjioEqDzZUI76fDGkOVQDmAExru/Yr20jxYpvmE+0//39GwP0HMU4v
3/GNNvshJtowtIyAehJNQcAaqc8A7kLo3o5jv6xrmhvWpfkxCmnMMHS6tEKgjfBm
2fhDc6PZJJtixcR4jVxo6u1cdcdMvCmAf+KPLj4KiMcouGj5QVpXJLaB7pHGDksf
FAuROrd2OHGOCb++gNZPriNrsU4tEFNjhp+m3OYJUS8GoVcym+oNjdnEBB2rADyf
S8bhGnEa2/fBHJ8PlnvrBGMGqC2i3q2Q7ECxEluKGXgWtOMhLmSquq4N8896EFOT
zr5UnBrv9kzIGGjfbMw6ALSXAQ9UhPD3Jm6YpvkGJfSN6o5ZvLlFG9XeVgqrpBmJ
l6UL5Nhrx9Q6LEwCpjz62PWL8bI7djn3ueFZGq+EzYnCvGEvpqw/+0ga22MqNK9D
W02TJQO6liARz90GR1XWLbndqmFjhBx3VNg0s5V2EJIYBFptNp7kCRVl/3OAw4Lh
JjA14DJSiv2xlyI6ZBVm1j/IiyfakZdBnlE6cmSom3YTGSPj7C8=
=cDbk
-----END PGP SIGNATURE-----
Merge tag 'riscv-sophgo-dt-for-v6.19' of https://github.com/sophgo/linux into soc/dt
RISC-V Devicetrees for v6.19
Sophgo:
For CV18xx serials:
Add top syscon device related DTS change, the top system
controller provides register access to configure some
misc modules, such as usb2 phy and a dma multiplexer.
For SG2042:
There are two changes. The first one is to add DTS
definition for PCIe controllers for SoC SG2042 and
boards such as Pioneerbox/EVB_V1/EVB_V2 uses SG2042.
The second one is to add DTS to support SPI-NOR flash
controllers for this SoC and the same for related boards.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* tag 'riscv-sophgo-dt-for-v6.19' of https://github.com/sophgo/linux:
riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2
riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1
riscv: dts: sophgo: Enable SPI NOR node for PioneerBox
riscv: dts: sophgo: Add SPI NOR node for SG2042
riscv: dts: sophgo: Add USB support for cv18xx
riscv: dts: sophgo: Add syscon node for cv18xx
dt-bindings: soc: sophgo: add TOP syscon for CV18XX/SG200X series SoC
riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
riscv: sophgo: dts: enable PCIe for PioneerBox
riscv: sophgo: dts: add PCIe controllers for SG2042
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Highlights:
-----------
- MPU:
- STM32MP13:
- Add and enable the ARM SMC watchdog to use IWDG1 in the secure
world.
- STMP32MP15:
- Phytec SOM: Fix STMPE811 touchscreen
- LXA: drop unnecessary vusb_d/a-supply as already defined by
"phy-supply" and "vdda1v8-supply".
- STM32MP23:
- Use the RIFSC as an access controler (firewall) as it is done
for STM32MP25 and STM32MP23.
- STM32MP25:
- Add OSPI memory region name.
- Add I/O synchronization properties to satisfy RGMII
specification.
-----BEGIN PGP SIGNATURE-----
iQJRBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmkcLpIdHGFsZXhhbmRy
ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIW6nw/6A/PBU5C/oRIRv/ZP
CDbmq9mI0g1pkFiXA8nlPgiKE1VF+1xl8cmqKAfl0ntKg4m3zzeVjaVlnNPKUP9J
6C6SDXWaJrGweLc4rOyrFdBgyv8D6NSZvbC6/8yFOy+Yj5ls9LDVpjDpA+1TUnxz
s6B1YS/mrNcyq1jUpCmCjGdA1vtK2/kPxweENXqjMELpRO/X5bUYj5xxTZtDK0aC
FDwW36CCppoHVGES4Gu/5TKhhNsl/qlEgTLf/f3aDbJh3LsowpYdOcTUilOl2cCE
Ms20Y3cYLOMsTkK9idsOboQgJxalVVuLZ/mGL+BIWxoWp+y/IAdk3WTHvkFcUCqU
N1U4CqDCp+3TYmXNiedcClghQsJb5zmwh6kGGE9gMU1BhOWW873qNN+X6VOXszrl
CTCsx9ybXa0xcsy+ne+YOLKxa0rkKRpCg7SfirmZ5IobhNXLRfw7VpLk9asAr1qk
5aJdek+sdFIgQiuXGY1ZiSmcH1lTiQtWOH6Zy2Hy96lFs6NYvfOihJZn4T9cfMHi
RYyzWN11IdUbh3eaSuYb9bJoxH9SlziboXnln2LruRa73vtxvmw84CFIk2q0pVS/
hARQ9b67l7ktWCWkcGWr65H3tF93YivhOBIKm9SYjxMctoV4rX/gOPRMDV3At6As
sLWxeA/sy5Y4Ul10H+LKYQexFhs=
=iYLR
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgw1YACgkQmmx57+YA
GNnLoQ//eRHBSHu1OZ91nDtsGE3G3msy5mrpqVjM6jvanK5TU1KI1h1n/TRUfK4v
n7vCELIAuImjrYUFu0HtbKZ2axdRcnlAS7Jj2KD21SdT8gXG/C4dor5gvdZe7dYH
ArFusLEV0NeG/6kMUs84J1Rh1u77TfnNi7+wQtSuhu9RV/0qL91Mtpom3NlzZOzS
7iIh1IK4RtoiJWbnj+LUFMdTke2kLb6Y+n2IDGyEoSPBWUjmsnyhk7EJtnN/t2JZ
CpjNFYgaqQvtA5dBIwGnaL2V8Trt9v65XfbOorH6dmm1v4BhpU3O/SN3d/nA9/et
NYnQSavU4yr/isrhvJsys2lKTFk34xpbVe4+Derkt5+aONWy0/BBL1D2rmQwAor0
bYpqK2WfoJ6O0XWMLGqHbYi4KsZqIFn/Gak6xRaxsdEMfJDMCqT/v/uu6MjNGioY
8EJTdzn5Y5K2syObQ/XknF2/2WPubY+ftjBFh2WUoL39JIn5nzeDuyH1XXirQ2Sp
2d4/D9uai/SAGVderH/5a1NyOr9B9gTr4gneWIdvTWYFeYQdk49BNwe4+DND40XD
8ey2XLL0aEfpeQNc5Q5P2wuaFMsqMI4lvQF/hCkfVdSmY1am7x9FuWjM8VwuHeg9
w/jv7RB39pQCobr5BhlOOKY+NX76MMf74Hd9iS8RQNQBGpgVFi8=
=dzuB
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.19, round 1
Highlights:
-----------
- MPU:
- STM32MP13:
- Add and enable the ARM SMC watchdog to use IWDG1 in the secure
world.
- STMP32MP15:
- Phytec SOM: Fix STMPE811 touchscreen
- LXA: drop unnecessary vusb_d/a-supply as already defined by
"phy-supply" and "vdda1v8-supply".
- STM32MP23:
- Use the RIFSC as an access controler (firewall) as it is done
for STM32MP25 and STM32MP23.
- STM32MP25:
- Add OSPI memory region name.
- Add I/O synchronization properties to satisfy RGMII
specification.
* tag 'stm32-dt-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
arm64: dts: st: set RIFSC as an access controller on stm32mp21x platforms
ARM: dts: stm32: add the IWDG2 interrupt line in stm32mp131.dtsi
ARM: dts: stm32: enable the ARM SMC watchdog node in stm32mp135f-dk
ARM: dts: stm32: add the ARM SMC watchdog in stm32mp131.dtsi
ARM: dts: stm32: add iwdg1 node in stm32mp131.dtsi
arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsi
arm64: dts: st: Add memory-region-names property for stm32mp257f-ev1
ARM: dts: stm32: lxa: drop unnecessary vusb_d/a-supply
ARM: dts: stm32: stm32mp157c-phycore: Fix STMPE811 touchscreen node properties
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
FriendlyElec NanoPi R76S
Interesting archeological addition: RK3368 (2015) gets display
output afterall.
New peripherals: vicap on px30 and rk356x, PCIe Gen2x1 on RK3528,
use actual clock-ids for SCMI clocks - not hardcoded numbers,
CQE support for the eMMC on RK3588.
As well as a number of enablements for individual boards.
For example enablement for the now usable NPU.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmkbnhoQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgRQFB/0VpxuWvUfs4FFNI4yB+UgN3+lvY3Y4tdZQ
4cQg9QuwhMqmiNLc/uEUEjMiET0Yqw1ycIVzGXhfyw16htw2X1X+Y+gJC/0rakS9
Eyk/jDBGi7/rFarVwZMeOxl07DKfQpiSumAWFyz1ww8U19YeXNY5UiXXIq4811Zn
z1yJddMjLJi8vlHGRrVD4L7pwhrppEdFKihPaaQfFaTDk3SwXNEk7I+hjzt3v94r
syURDuAMHZ2Yriz4mcp2bMtB63NN5JR6/WOHzXEHv9jueJ2vZvpxs1075vQCSq5V
7ckoFTLftSbZE1N3CGHmBnLZX4gEoUgRclxlbzIQ7LP55nk91IFJ
=uKf+
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgwwsACgkQmmx57+YA
GNn8BxAAnklFUJ+C2KumNWLKI+Gi3Nl/rjaecr4ijvyAQXr3bZK+sQ9fPniZKznx
R5vyufEhlbs5GqUQ8DjH1CgeqZHZR9Wt6gLjgJwt3CJsIzr6bDssUaVcPSxneCtF
S94FxJUSmLgmvxC8/qeXGuWpSb1SuAFWNAL8OXon7raydL6mJFhoybDsfRObyIVi
e8KTu1jOEgpZQmWcR9cCctdVNrLMKIvopFvf8iOEeAOCv5ZAeR9vGy3HtPQbSGci
9zSVs9qjrXtXHn0L3sl1If0kz+Sf1i6HkAjzc8Us5nNA7WmxP7XdY5DCvkbvjcfe
kbj+30HFLkTGPncZ8rOXRfa3nkdV9QwRDGqixcZBguACqnlRBR7QzYWdoxKcMLao
SKiPKmrRVNRv/CUUggXO4nxbDs33VzjZagBfuMWKzbMecodWq52nAzd/l6WuzRu9
tBPYlVI3E9EvnYNuhTL4kQbqirkanxkiMP4enXw3xHdGs9muEYUaOcR1IE+pITSm
BP4aVDbDAOyjtMV6Yfu/dd7rQAO4NAeZkknEhB+wJ1dOcdl+iwT9vtc+v99ZVI7m
sfJjBMES70ZpitVj/p1QddqBtlokzd0xplXgr6x69b/hPPRkTpvN8n4aq4+O+Wo1
ECSBvH5gECe1MSJgokohj0TpInv5OwEhQSSbNBkVYH481QiN+YI=
=eKTU
-----END PGP SIGNATURE-----
Merge tag 'v6.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: 9Tripod X3568, 100ASK DShanPi A1, LinkEase EasePi R1,
FriendlyElec NanoPi R76S
Interesting archeological addition: RK3368 (2015) gets display
output afterall.
New peripherals: vicap on px30 and rk356x, PCIe Gen2x1 on RK3528,
use actual clock-ids for SCMI clocks - not hardcoded numbers,
CQE support for the eMMC on RK3588.
As well as a number of enablements for individual boards.
For example enablement for the now usable NPU.
* tag 'v6.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (43 commits)
arm64: dts: rockchip: add vicap node to rk356x
arm64: dts: rockchip: add the vip node to px30
arm64: dts: rockchip: fixes audio for 100ASK DshanPi A1
arm64: dts: rockchip: fixes vcc3v3_s0 supply for 100ASK DshanPi A1
arm64: dts: rockchip: fixes ethernet for 100ASK DshanPi A1
arm64: dts: rockchip: fixes regulator for 100ASK DshanPi A1
arm64: dts: rockchip: correct assigned-clock-rates spelling on 2 boards
arm64: dts: rockchip: clean up devicetree for 9Tripod X3568 v4
arm64: dts: rockchip: Enable USB-C DP Alt for Indiedroid Nova
arm64: dts: rockchip: add eMMC CQE support for rk3588
arm64: dts: rockchip: enable HDMI audio on Rock 5 ITX
arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 3C
arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 5A
arm64: dts: rockchip: Move the EEPROM to correct I2C bus on Radxa ROCK 5A
arm64: dts: rockchip: use SCMI clock id for gpu clock on rk356x
arm64: dts: rockchip: Remove sdmmc max-frequency on RK3588S EVB1 board
arm64: dts: rockchip: Remove sdmmc max-frequency for Radxa ROCK 5 ITX/5B/5B+/5T
arm64: dts: rockchip: Switch microSD card detect to gpio on Radxa ROCK 5 ITX/5C
arm64: dts: rockchip: Add devicetree for the 9Tripod X3568 v4
dt-bindings: arm: rockchip: Add 9Tripod X3568 series
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The commit1 def98c84b6 ("workqueue: Fix spurious sanity check failures
in destroy_workqueue()") tries to fix spurious sanity check failures by
stopping send_mayday() via setting wq->rescuer to NULL.
But it fails to stop the pwq->mayday_node requeuing in the rescuer, and
the commit2 e66b39af00 ("workqueue: Fix pwq ref leak in
rescuer_thread()") fixes it by checking wq->rescuer which is the result
of commit1.
Both commits together really fix spurious sanity check failures caused
by the rescuer, but they both use a convoluted method by relying on
wq->rescuer state rather than the real count of work items.
Actually __WQ_DESTROYING and drain_workqueue() together already stop
send_mayday() by draining all the work items and ensuring no new work
item requeuing.
And the more proper fix to stop the pwq->mayday_node requeuing in the
rescuer is from commit3 4f3f4cf388 ("workqueue: avoid unneeded
requeuing the pwq in rescuer thread") and renders the checking of
wq->rescuer in commit2 unnecessary.
So __WQ_DESTROYING, drain_workqueue() and commit3 together fix spurious
sanity check failures introduced by the rescuer.
Just remove the convoluted code of using wq->rescuer.
Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
If the pwq does not need rescue (normal workers have been created or
become available), the rescuer can immediately move on to other stalled
pwqs.
Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Move the code to assign work to rescuer and assign_rescuer_work().
Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Extend the logic of handling CMCI storms to AMD threshold interrupts.
Rely on the similar approach as of Intel's CMCI to mitigate storms per CPU and
per bank. But, unlike CMCI, do not set thresholds and reduce interrupt rate on
a storm. Rather, disable the interrupt on the corresponding CPU and bank.
Re-enable back the interrupts if enough consecutive polls of the bank show no
corrected errors (30, as programmed by Intel).
Turning off the threshold interrupts would be a better solution on AMD systems
as other error severities will still be handled even if the threshold
interrupts are disabled.
[ Tony: Small tweak because mce_handle_storm() isn't a pointer now ]
[ Yazen: Rebase and simplify ]
[ Avadhut: Remove check to not clear bank's bit in mce_poll_banks and fix
checkpatch warnings. ]
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/20251121190542.2447913-3-avadhut.naik@amd.com
-Wflex-array-member-not-at-end was introduced in GCC-14, and we are
getting ready to enable it, globally.
Move the conflicting declaration to the end of the corresponding
structure. Notice that struct iommufd_vevent is a flexible
structure, this is a structure that contains a flexible-array
member.
Fix the following warning:
drivers/iommu/iommufd/iommufd_private.h:621:31: warning: structure containing a flexible array member is not at the end of another structure [-Wflex-array-member-not-at-end]
Link: https://patch.msgid.link/r/aRHOAwpATIE0oajj@kspp
Signed-off-by: "Gustavo A. R. Silva" <gustavoars@kernel.org>
Fixes: e36ba5ab80 ("iommufd: Add IOMMUFD_OBJ_VEVENTQ and IOMMUFD_CMD_VEVENTQ_ALLOC")
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
One of the requirements for counted_by annotations is that the counter
member must be initialized before the first reference to the
flexible-array member.
Move the vevent->data_len = data_len; initialization to before the
first access to flexible array vevent->event_data.
Link: https://patch.msgid.link/r/aRL7ZFFqM5bRTd2D@kspp
Cc: stable@vger.kernel.org
Fixes: e8e1ef9b77 ("iommufd/viommu: Add iommufd_viommu_report_event helper")
Signed-off-by: "Gustavo A. R. Silva" <gustavoars@kernel.org>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Currently, when a CMCI storm detected on a Machine Check bank, subsides, the
bank's corresponding bit in the mce_poll_banks per-CPU variable is cleared
unconditionally by cmci_storm_end().
On AMD SMCA systems, this essentially disables polling on that particular bank
on that CPU. Consequently, any subsequent correctable errors or storms will not
be logged.
Since AMD SMCA systems allow banks to be managed by both polling and
interrupts, the polling banks bitmap for a CPU, i.e., mce_poll_banks, should
not be modified when a storm subsides.
Fixes: 7eae17c4ad ("x86/mce: Add per-bank CMCI storm mitigation")
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251121190542.2447913-2-avadhut.naik@amd.com
Extends device tree support to include the AST2700 chip variant by
adding its compatible string to the device match table.
The AST2700 PWM/TACH hardware is compatible with the existing driver
implementation used for AST2600.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20251120-upstream_pwm_tach-v3-2-eaa2f9b300a2@aspeedtech.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Adds support for the AST2700 PWM/Tach controller by extending the
compatible string enumeration in the device tree binding.
The AST2700 PWM/Tach hardware is compatible with the existing binding
schema and requires no additional properties or modifications beyond
the new compatible string.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20251120-upstream_pwm_tach-v3-1-eaa2f9b300a2@aspeedtech.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
