Commit graph

96,072 commits

Author SHA1 Message Date
Joe Perches
ddeaa6379d sunrpc & nfs: Add and use dprintk_cont macros
Allow line continuations to work properly with KERN_CONT.

Signed-off-by: Joe Perches <joe@perches.com>
[Anna: Add fallback dprintk_cont() for when CONFIG_SUNRPC_DEBUG=n]
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
2017-01-30 13:14:50 -05:00
Sean Young
a92def1bec [media] ir-rx51: port to rc-core
This driver was written using lirc since rc-core did not support
transmitter-only hardware at that time. Now that it does, port
this driver.

Compile tested only.

Signed-off-by: Sean Young <sean@mess.org>
Cc: Timo Kokkonen <timo.t.kokkonen@iki.fi>
Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 14:25:04 -02:00
Andi Shyti
d34aee1018 [media] rc-core: add support for IR raw transmitters
IR raw transmitter driver type is specified in the enum
rc_driver_type as RC_DRIVER_IR_RAW_TX which includes all those
devices that transmit raw stream of bit to a receiver.

The data are provided by userspace applications, therefore they
don't need any input device allocation, but still they need to be
registered as raw devices.

Suggested-by: Sean Young <sean@mess.org>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Sean Young <sean@mess.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 14:14:12 -02:00
Andi Shyti
0f7499fddb [media] rc-main: assign driver type during allocation
The driver type can be assigned immediately when an RC device
requests to the framework to allocate the device.

This is an 'enum rc_driver_type' data type and specifies whether
the device is a raw receiver or scancode receiver. The type will
be given as parameter to the rc_allocate_device device.

Change accordingly all the drivers calling rc_allocate_device()
so that the device type is specified during the rc device
allocation. Whenever the device type is not specified, it will be
set as RC_DRIVER_SCANCODE which was the default '0' value.

Suggested-by: Sean Young <sean@mess.org>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Sean Young <sean@mess.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 13:59:57 -02:00
James Hogan
f423ccc1a3 [media] rc: rc-core: Add support for encode_wakeup drivers
Add support in rc-core for drivers which implement the wakeup scancode
filter by encoding the scancode using the raw IR encoders. This is by
way of rc_dev::encode_wakeup which should be set to true and
rc_dev::allowed_wakeup_protocols should be set to the raw IR encoders.

We also do not permit the mask to be set as we cannot generate IR
which would match that.

Signed-off-by: James Hogan <james@albanarts.com>
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Sean Young <sean@mess.org>
Cc: David Härdeman <david@hardeman.nu>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 13:55:45 -02:00
James Hogan
3875233d0b [media] rc: rc-ir-raw: Add scancode encoder callback
Add a callback to raw ir handlers for encoding and modulating a scancode
to a set of raw events. This could be used for transmit, or for
converting a wakeup scancode to a form that is more suitable for raw
hardware wake up filters.

Signed-off-by: James Hogan <james@albanarts.com>
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Sean Young <sean@mess.org>
Cc: David Härdeman <david@hardeman.nu>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 13:46:55 -02:00
Pavel Belous
94842b4fc4 net: ethtool: add support for 2500BaseT and 5000BaseT link modes
This patch introduce support for 2500BaseT and 5000BaseT link modes.
These modes are included in the new IEEE 802.3bz standard.

Signed-off-by: Pavel Belous <pavel.s.belous@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-01-30 10:14:28 -05:00
Joerg Roedel
ce273db0ff Merge branch 'iommu/iommu-priv' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/core 2017-01-30 16:05:18 +01:00
Joerg Roedel
aac7d39f20 Merge branch 'for-joerg/arm-smmu/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu 2017-01-30 16:01:16 +01:00
Joerg Roedel
93fa6cf60a Merge branch 'iommu/guest-msi' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/core 2017-01-30 15:58:47 +01:00
Sean Young
8c34b5c4c8 [media] rc: raw IR drivers cannot handle cec, unknown or other
unknown and other are for IR protocols for which we have no decoder,
so the raw IR drivers have no chance of generating them. cec is not
an IR protocol.

Signed-off-by: Sean Young <sean@mess.org>
Cc: Jiri Kosina <jikos@kernel.org>
Cc: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 12:40:50 -02:00
Marc Zyngier
08d85f3ea9 irqdomain: Avoid activating interrupts more than once
Since commit f3b0946d62 ("genirq/msi: Make sure PCI MSIs are
activated early"), we can end-up activating a PCI/MSI twice (once
at allocation time, and once at startup time).

This is normally of no consequences, except that there is some
HW out there that may misbehave if activate is used more than once
(the GICv3 ITS, for example, uses the activate callback
to issue the MAPVI command, and the architecture spec says that
"If there is an existing mapping for the EventID-DeviceID
combination, behavior is UNPREDICTABLE").

While this could be worked around in each individual driver, it may
make more sense to tackle the issue at the core level. In order to
avoid getting in that situation, let's have a per-interrupt flag
to remember if we have already activated that interrupt or not.

Fixes: f3b0946d62 ("genirq/msi: Make sure PCI MSIs are activated early")
Reported-and-tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/1484668848-24361-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2017-01-30 15:18:56 +01:00
Sean Young
0751d33c27 [media] rc: change wakeup_protocols to list all protocol variants
For IR wakeup, a driver has to program the hardware to wakeup at a
specific IR sequence, so it makes no sense to allow multiple wakeup
protocols to be selected. In the same manner the sysfs interface only
allows one scancode to be provided.

In addition, we need to know the specific variant of the protocol.

In short, these changes are made to the wakeup_protocols sysfs entry:
 - list all the protocol variants rather than the protocol groups,
   e.g. "nec nec-x nec-32" rather than just "nec".
 - only allow one protocol variant to be selected rather than multiple
 - wakeup_filter can only be set once a protocol has been selected in
   wakeup_protocols.

This is an API change, however the only user of this API is the img-ir,
but the wakeup code was never merged to mainline, so it was never used.

Signed-off-by: Sean Young <sean@mess.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Sifan Naeem <sifan.naeem@imgtec.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 12:15:12 -02:00
Sean Young
0fcd3f0a3f [media] rc5x: document that this is the 20 bit variant
There are many variants of extended rc5. This implements the 20 bit
version.

Signed-off-by: Sean Young <sean@mess.org>
Cc: David Härdeman <david@hardeman.nu>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 12:10:45 -02:00
Sean Young
517b500713 [media] cxusb: port to rc-core
The d680_dmb keymap has some new new mappings.

Tested-by: Vincent McIntyre <vincent.mcintyre@gmail.com>
Signed-off-by: Sean Young <sean@mess.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-01-30 11:50:32 -02:00
Marc Zyngier
9d93dc1c96 arm/arm64: KVM: Get rid of KVM_MEMSLOT_INCOHERENT
KVM_MEMSLOT_INCOHERENT is not used anymore, as we've killed its
only use in the arm/arm64 MMU code. Let's remove the last artifacts.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:38 +00:00
Vijaya Kumar K
d017d7b0bd KVM: arm/arm64: vgic: Implement VGICv3 CPU interface access
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
It is used to identify the cpu for registers access.

The VM that supports SEIs expect it on destination machine to handle
guest aborts and hence checked for ICC_CTLR_EL1.SEIS compatibility.
Similarly, VM that supports Affinity Level 3 that is required for AArch64
mode, is required to be supported on destination machine. Hence checked
for ICC_CTLR_EL1.A3V compatibility.

The arch/arm64/kvm/vgic-sys-reg-v3.c handles read and write of VGIC
CPU registers for AArch64.

For AArch32 mode, arch/arm/kvm/vgic-v3-coproc.c file is created but
APIs are not implemented.

Updated arch/arm/include/uapi/asm/kvm.h with new definitions
required to compile for AArch32.

The version of VGIC v3 specification is defined here
Documentation/virtual/kvm/devices/arm-vgic-v3.txt

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:25 +00:00
Vijaya Kumar K
5fb247d79c KVM: arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.

Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT and ICH_VMCR_CTLR_MASK macros and instead
use ICH_VMCR_EOI* and ICH_VMCR_CBPR* macros.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:21 +00:00
Vijaya Kumar K
5c34153704 irqchip/gic-v3: Add missing system register definitions
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:20 +00:00
Linus Walleij
7f36f5d11c Linux 4.10-rc6
-----BEGIN PGP SIGNATURE-----
 
 iQEcBAABAgAGBQJYjmvUAAoJEHm+PkMAQRiGHIoH/3VaTj7cCJZDnWZ2Wi2enWip
 f17zj0oAkFxuSx8XEVD5BKqMfGBCBjPNPwURysfcFVoSHNtHjbEr44VxiPfQj5s2
 N+znVm5P9qlFuRA+7dgYUyEKOqcTgyT9jFNpvPF6bgMZDfJoB/wo53UU4lo3drcx
 cRe6OT4fEpAbtgbl73kIjOreBRr7oxlMPVEjCVRdL7ssCg+iqow0MEHcSoO7jmtj
 tu8hwwBMNh5B0yJRCJKV7Edc1+GHK57ju6rnGr5S2rwnR31omLpvnHJx0Ya6NVCZ
 yV3KGQeWm13ifbumMddEnAL61x2hOIzX//BqaZKdy258YPohkNtD8oacnjHnLMc=
 =5Rs+
 -----END PGP SIGNATURE-----

Merge tag 'v4.10-rc6' into devel

Linux 4.10-rc6

Resolved conflicts in:
	drivers/pinctrl/pinctrl-amd.c
	drivers/pinctrl/samsung/pinctrl-exynos.c
2017-01-30 14:39:20 +01:00
David Carrillo-Cisneros
1fd7e41699 perf/core: Remove perf_cpu_context::unique_pmu
cpuctx->unique_pmu was originally introduced as a way to identify cpuctxs
with shared pmus in order to avoid visiting the same cpuctx more than once
in a for_each_pmu loop.

cpuctx->unique_pmu == cpuctx->pmu in non-software task contexts since they
have only one pmu per cpuctx. Since perf_pmu_sched_task() is only called in
hw contexts, this patch replaces cpuctx->unique_pmu by cpuctx->pmu in it.

The change above, together with the previous patch in this series, removed
the remaining uses of cpuctx->unique_pmu, so we remove it altogether.

Signed-off-by: David Carrillo-Cisneros <davidcc@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul Turner <pjt@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: Vince Weaver <vince@deater.net>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/20170118192454.58008-3-davidcc@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-30 12:01:14 +01:00
David Carrillo-Cisneros
058fe1c044 perf/core: Make cgroup switch visit only cpuctxs with cgroup events
This patch follows from a conversation in CQM/CMT's last series about
speeding up the context switch for cgroup events:

  https://patchwork.kernel.org/patch/9478617/

This is a low-hanging fruit optimization. It replaces the iteration over
the "pmus" list in cgroup switch by an iteration over a new list that
contains only cpuctxs with at least one cgroup event.

This is necessary because the number of PMUs have increased over the years
e.g modern x86 server systems have well above 50 PMUs.

The iteration over the full PMU list is unneccessary and can be costly in
heavy cache contention scenarios.

Below are some instrumentation measurements with 10, 50 and 90 percentiles
of the total cost of context switch before and after this optimization for
a simple array read/write microbenchark.

  Contention
    Level    Nr events      Before (us)            After (us)       Median
  L2    L3     types      (10%, 50%, 90%)       (10%, 50%, 90%     Speedup
  --------------------------------------------------------------------------
  Low   Low       1       (1.72, 2.42, 5.85)    (1.35, 1.64, 5.46)     29%
  High  Low       1       (2.08, 4.56, 19.8)    (1720, 2.20, 13.7)     51%
  High  High      1       (2.86, 10.4, 12.7)    (2.54, 4.32, 12.1)     58%

  Low   Low       2       (1.98, 3.20, 6.89)    (1.68, 2.41, 8.89)     24%
  High  Low       2       (2.48, 5.28, 22.4)    (2150, 3.69, 14.6)     30%
  High  High      2       (3.32, 8.09, 13.9)    (2.80, 5.15, 13.7)     36%

where:

  1 event type  = cycles
  2 event types = cycles,intel_cqm/llc_occupancy/

   Contention L2 Low: workset  <  L2 cache size.
                 High:  "     >>  L2   "     " .
   Contention L3 Low: workset of task on all sockets  <  L3 cache size.
                 High:   "     "   "   "   "    "    >>  L3   "     " .

   Median Speedup is (50%ile Before - 50%ile After) /  50%ile Before

Unsurprisingly, the benefits of this optimization decrease with the number
of cpuctxs with a cgroup events, yet, is never detrimental.

Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: David Carrillo-Cisneros <davidcc@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul Turner <pjt@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: Vince Weaver <vince@deater.net>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/20170118192454.58008-2-davidcc@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-30 12:01:13 +01:00
Linus Walleij
4404d7d821 mtd: nand: fsmc: remove stale non-DT probe path
The FSMC driver has an execution path and a header file in
<linux/mtd/fsmc.h> that serves to support passing in platform
data through board files, albeit no upstream users of this
mechanism exist.

The header file also contains function headers for functions that
do not exist in the kernel.

Delete this and move the platform data struct, parsing and
handling into the driver, assume we are using OF and make the
driver depend on OF, remove the ifdefs making that optional.

Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-01-30 11:50:30 +01:00
Randy Dunlap
61babe9439 mtd: nand: fix nand.h kernel-doc warnings
Fix kernel-doc warnings in <linux/mtd/nand.h>:

..//include/linux/mtd/nand.h:658: warning: No description found for parameter 'tCEH_min'
..//include/linux/mtd/nand.h:877: warning: No description found for parameter 'data_interface'

Fixes: eee64b700e ("mtd: nand: Introduce nand_data_interface")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-01-30 11:50:30 +01:00
Ingo Molnar
ae5112a825 Merge branch 'perf/urgent' into perf/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-30 11:47:00 +01:00
Thomas Gleixner
9556ad6ad0 Merge branch 'fortglx/4.11/time' of https://git.linaro.org/people/john.stultz/linux into timers/core
- Remove unused functions
 - Document udelay inaccuracy
 - Remove posix timer data from task struct when posix timers are off
2017-01-30 11:22:39 +01:00
Daniel Vetter
e6e7b48b29 drm: Don't race connector registration
I was under the misconception that the sysfs dev stuff can be fully
set up, and then registered all in one step with device_add. That's
true for properties and property groups, but not for parents and child
devices. Those must be fully registered before you can register a
child.

Add a bit of tracking to make sure that asynchronous mst connector
hotplugging gets this right. For consistency we rely upon the implicit
barriers of the connector->mutex, which is taken anyway, to ensure
that at least either the connector or device registration call will
work out.

Mildly tested since I can't reliably reproduce this on my mst box
here.

Reported-by: Dave Hansen <dave.hansen@intel.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1484237756-2720-1-git-send-email-daniel.vetter@ffwll.ch
2017-01-30 10:17:32 +01:00
Daniel Vetter
4e5b54f127 drm: prevent double-(un)registration for connectors
If we're unlucky then the registration from a hotplugged connector
might race with the final registration step on driver load. And since
MST topology discover is asynchronous that's even somewhat likely.

v2: Also update the kerneldoc for @registered!

v3: Review from Chris:
- Improve kerneldoc for late_register/early_unregister callbacks.
- Use mutex_destroy.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218133545.2106-1-daniel.vetter@ffwll.ch
(cherry picked from commit e73ab00e9a)
2017-01-30 10:17:17 +01:00
Hans de Goede
b526a31426 pwm: Try to load modules during pwm_get()
Add a module name string to the pwm_lookup struct and if specified try
to load the module using request_module() if pwmchip_find_by_name() is
unable to find the PWM chip.

This is a last resort to work around drivers that can't - and can't be
made to - deal with deferred probe.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[thierry.reding@gmail.com: rename new macro, reword commit message]
[thierry.reding@gmail.com: add comment explaining use-case]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2017-01-30 09:36:42 +01:00
Viresh Kumar
7034764a1e PM / OPP: Add 'struct kref' to struct dev_pm_opp
Add kref to struct dev_pm_opp for easier accounting of the OPPs.

Note that the OPPs are freed under the opp_table->lock mutex only.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2017-01-30 09:22:21 +01:00
Viresh Kumar
fa30184d19 PM / OPP: Return opp_table from dev_pm_opp_set_*() routines
Now that we have proper kernel reference infrastructure in place for OPP
tables, use it to guarantee that the OPP table isn't freed while being
used by the callers of dev_pm_opp_set_*() APIs.

Make them all return the pointer to the OPP table after taking its
reference and put the reference back with dev_pm_opp_put_*() APIs.

Now that the OPP table wouldn't get freed while these routines are
executing after dev_pm_opp_get_opp_table() is called, there is no need
to take opp_table_lock. Drop them as well.

Remove the rcu specific comments from these routines as they aren't
relevant anymore.

Note that prototypes of dev_pm_opp_{set|put}_regulators() were already
updated by another patch.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2017-01-30 09:22:21 +01:00
Viresh Kumar
f067a982ce PM / OPP: Add 'struct kref' to OPP table
Add kref to struct opp_table for easier accounting of the OPP table.

Note that the new routine dev_pm_opp_get_opp_table() takes the reference
from under the opp_table_lock, which guarantees that the OPP table
doesn't get freed unless dev_pm_opp_put_opp_table() is called for the
OPP table.

Two separate release mechanisms are added: locked and unlocked. In
unlocked version the routines aren't required to take/drop
opp_table_lock as the callers have already done that. This is required
to avoid breaking git bisect, otherwise we may get lockdeps between
commits. Once all the users of OPP table are updated the unlocked
version shall be removed.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2017-01-30 09:22:20 +01:00
Rafael J. Wysocki
858a0d7eb5 Merge back earlier suspend/hibernation changes for v4.11. 2017-01-30 09:00:02 +01:00
Chen-Yu Tsai
783ab76ae5 clk: sunxi-ng: Add A80 Display Engine CCU
With the A80 SoC, Allwinner grouped and moved some subsystem specific
clock controls to a separate address space, and possibly separate
hardware block.

One such subsystem is the display engine. The main clock control unit
now only has 1 set of bus gate, dram gate, module clock, and reset
control for the entire display subsystem. These feed into a secondary
clock control unit, which has controls for each individual module
of the display pipeline. This block is not documented in the user
manual. Allwinner's kernel was used as the reference.

Add support for the display engine clock controls found on the A80.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:38:30 +01:00
Chen-Yu Tsai
439b65c4bb clk: sunxi-ng: Add A80 USB CCU
Add support for the USB clock controls found on the A80.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:37:51 +01:00
Chen-Yu Tsai
b8eb71dcdd clk: sunxi-ng: Add A80 CCU
Add support for the main clock unit found in the A80. Some clocks were
not documented in the released user manual, but were found in the
official kernel from Allwinner. These include controls for the I2S,
SPDIF, SATA, and eDP blocks.

Note that on the A80, some subsystems have separate clock controllers
downstream of the main clock unit. These include the MMC, USB, and
display engine subsystems.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:37:30 +01:00
Olof Johansson
1096ffd75a Continuation of improvements for Exynos PM drivers for v4.11:
1. Add support for Exynos5433 to Power Management Unit (PMU) and Power
    Domains drivers.
 2. Cleanups of duplicated and unused defines.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYjkgyAAoJEME3ZuaGi4PXtVoP/3TJmoi6z6Qmxc9Ux6ATmNKO
 KhEM2u5si2psK6DD6YNrmC9st3C2dnhiej6g6KG3dK7WVrSQigjZCCQurFWccx0M
 BE5Dr/A9hhJtwLOdLwCcS1Fywv0aFuCEh2F6Jgq6lCs1Z/EFuxZ9DflDLdimakvc
 18hyC2kLN3cb7ME10Zr+YMaG5GaoimP5mkUX1czJcaSWtVoXFCW6H9j4QQg2geE1
 0sPBjKx4bHEah8LfsckijdwyamE7wGVzDslq+YVAMqPstW781FSFAlNGe2cc+Xlj
 GPJfgtgVZYdu4meRZwbli9T4RslsqULPYDUFRoq+ffp1Hrp7kXoBL5jFYK0W9gjD
 Sgm/oFGpymIY/GdwyTzYSHPeNxK8RtmNkC3WDY4JY6gn8BcK3mvK/4M9NAQw1fWn
 2A+eZjZr+AsyoNJtNk69mjYweSJmJ+pFBnni8ygrejq5FYfwVXD6OenvAxqQ7RDG
 aC2OuXhjr1BMoq5hiYen3Eh3b1Okftlu3f6/SVi2h8Ct5W4oK8c08dvbmpOYB3hk
 jeEMnh45PkoXHG7vMTU14euJVlTxhhTQ/hFSl21Ous6LdrxaZBQFsrszKma5wtvJ
 a9mAzonRJPXH/4Gt6kYOe90VDWp0SWFkOaA1zeIOdVnC0ifn7rZls6df6R6coKDY
 3g0X2xPhQiywSSa6Hq1T
 =pXm9
 -----END PGP SIGNATURE-----

Merge tag 'samsung-drivers-soc-pmu-4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers

Continuation of improvements for Exynos PM drivers for v4.11:
1. Add support for Exynos5433 to Power Management Unit (PMU) and Power
   Domains drivers.
2. Cleanups of duplicated and unused defines.

* tag 'samsung-drivers-soc-pmu-4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  soc: samsung: pmu: Remove duplicated define for ARM_L2_OPTION register
  soc: samsung: pmu: Remove unused and duplicated defines
  soc: samsung: pm_domains: Add new Exynos5433 compatible
  soc: samsung: pmu: Add dummy support for Exynos5433 SoC

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 21:18:44 -08:00
Olof Johansson
2a742e1b18 ZTE PM domain driver support for 4.11:
- It includes a series which adds DT bindings and PM domain driver for
    PCU (Power Control Unit) block found on ZTE ZX2967 family SoC.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJYjW7hAAoJEFBXWFqHsHzOCN8H/jVJo7Rnx4zwL8sx+2pjuceN
 ecTTu2l9U5Nh2Y1uRqDf914rquJteDNYoe0oWz71W7UxpJMl20X3zjfso7SWDqx8
 uSEgad6V/qHkgQQnLL9S9WdFQEGhfjVYvnMoVjBQEb1jpwdIm+nr8PIZ+Fqhh8u0
 3OLOjXk40PvzKcYwkxqeJQajP0pE6UFUOXQesolcCr+ilTvoqqQ9chPY4Jvsc7Qf
 ffC+ueSUymAhIqof2kEfy3PS5NA/ltQjokDpKjvU2+e3uJtM3qwstzt1kPCgX/d7
 azOuNNdif4hT2J26qIBG5H/wS/dFEvxnA0P4J/XUwkQ4FPRpa2Er1+F+03n5sPc=
 =XwPV
 -----END PGP SIGNATURE-----

Merge tag 'zte-pd-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers

ZTE PM domain driver support for 4.11:
 - It includes a series which adds DT bindings and PM domain driver for
   PCU (Power Control Unit) block found on ZTE ZX2967 family SoC.

* tag 'zte-pd-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: zte: pm_domains: Add support for zx296718
  soc: zte: pm_domains: Prepare for supporting ARMv8 zx2967 family
  soc: zte: Add header for PM domains specifiers
  MAINTAINERS: add zx2967 SoC drivers to ARM ZTE architecture
  dt-bindings: zte: add bindings document for zx2967 power domain controller

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 21:17:24 -08:00
Olof Johansson
18e738d767 Second Round of Renesas ARM Based SoC DT Updates for v4.11
Enhancements:
 * Add power-domains to mmcif on r7s72100 SoC
 * Add OSTM to rskrza1/r7s72100
 * Link ARM GIC to clock and clock domain on r8a774[35] SoCs
 
 Clean-up:
 * Correct SATA device status on r8a7779/marzen
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYicoiAAoJENfPZGlqN0+++P8P/REww60pI3KHlxzdU/WeMfMi
 VEyQCKXJ4x9HVNubJ1f9w8aJBYqSFLCJulYqk4yu1LZJNmTqqD/Z1xtk382z6vmr
 uDW3JUj5Vn8kX5FmobN8boU/al4ozildB6Z2r6blnhwC1w3/fZnY88U4PHnKZ9Y2
 dJDaYUsjPawf81vJu68MzyEkOXQBfrWrxGr0wdngdOY1BE0ahL7tMvPy3uAtXVC3
 YWSJXf25cxiDzDRbmnpMe1dz5nziOq9juaPnDiJCIi8L0Cuf1ZYpvLV2nzrA0MC2
 hX+aF94CH8niZW74FMWa8ijjuq7BbgDla9G0R37St29D7/C4c+1mI2cy3qUeJBAn
 PKNj+Cmjvrdg/4dFU2X5NaufDXE+wbjsZ8I07iftqhkH6c0EZle6adhAVSlLAQHo
 Kk7PRKvTLQV3YsItlW41w0Q13jfkBhtnW3SQtTYQDY88omHytcrM5/EqLdfQxNzQ
 6IEUjPuBLLufHfXL0OADAVFitOB6djT5qZDJcGFOcZ1Bh8Fx4+zY2kCpcIi/tAl1
 s66kkG8QUiekl0hYcIfviFhkksYmIGVLIrQ17cSB31FCf9jR6b3zUkpPWZChXHDc
 jReosGFSfvbxiTdllDyKrDW8CuMaFsc9K/HVMcsRDUwUcCvTdTDF2MruQ5svChyL
 axMDOW4cOiSqMko0i4lQ
 =5/D6
 -----END PGP SIGNATURE-----

Merge tag 'renesas-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Second Round of Renesas ARM Based SoC DT Updates for v4.11

Enhancements:
- Add power-domains to mmcif on r7s72100 SoC
- Add OSTM to rskrza1/r7s72100
- Link ARM GIC to clock and clock domain on r8a774[35] SoCs

Clean-up:
- Correct SATA device status on r8a7779/marzen

* tag 'renesas-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: r7s72100: add power-domains to mmcif
  ARM: dts: rskrza1: add ostm DT support
  ARM: dts: r7s72100: add ostm to device tree
  ARM: dts: r7s72100: add ostm clock to device tree
  ARM: dts: r8a7745: Link ARM GIC to clock and clock domain
  ARM: dts: r8a7743: Link ARM GIC to clock and clock domain
  ARM: dts: r8a7779, marzen: Fix sata device status

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 20:54:31 -08:00
Olof Johansson
c0d3245609 Non-urgent fixes for omaps for v4.11 merge window. These all are
fixes for things that have never worked or have been broken for
 a long time and nobody noticed:
 
 - Fix omap3 off mode pull defines
 
 - Allow multiple pdata quirks instead of just one
 
 - Fix am335x and dm814x scm syscon to probe children too
 
 - Fix compatible for ti81xx to allow use with 8250_omap as well
 
 - Fix 8250_omap on omap5 by adding HWMOD_SWSUP_SIDLE_ACT flag
 
 - Fix SoC detection for omap36/37 SoCs
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAliHdcARHHRvbnlAYXRv
 bWlkZS5jb20ACgkQG9Q+yVyrpXOdpA//cV9JLHoQWAheQIxPKcSC6bNANOJDik7I
 thKcbOmiH23xbLbOI/DoOY/jNfXIKHm67LUbfWRCljW03n2EaPgdaaM4Yar66MNC
 /n1JNqOF4ldetMb1uFw6Mlr5Jq44i4yZf6Q/0QwTN9pWnMBFj91nsKBSONrFEQJP
 snNtUwK1lSBHeVoOHVUujKHJJGpZvtclnPlzZ2Xqf1eDysfjQRrA1PAHljB8ScmY
 JfSVifZcR8MGMezEHbonimEH725Cwev/GuDJ3ADqBah1E/3ahRL3F9bkZnro9eqv
 0kPagVla+HSDS8SDzBYeUBwsUccYKx4haGGzQ5bHACbEtCGOgjO3wRdFNkCALnxG
 jcLerUI4DVPYYAuzowUK6gU60cErxIbVhMCxkDcslliFzuK4i9xVYhdPTnE/7pAN
 14dgNjz8drYm6SJHg4LWY9nq5UE2H3Gk5eWr52zlwhID2M0FJXCp2Fr51OocS/JB
 qrCLsuJCmtcxMEaI++iRf6b6OblfAV5bwpHOBX1QkZfz7GwhhKhK2ZERewTWWJS4
 eagdF4B+aw9zrRq/nLf09RMB4OjE+7OqvIVnA1MWxnDyfACcYuOodkXys4DxB7In
 z+3ToH3lwzqLP4Zi3enr7Bs669Hz2KWJzjf8WwfbDG3e9IEa9t5sLMBFtrVfPRG9
 qH53nlHABqQ=
 =SNQE
 -----END PGP SIGNATURE-----

Merge tag 'omap-for-v4.11/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical

Non-urgent fixes for omaps for v4.11 merge window. These all are
fixes for things that have never worked or have been broken for
a long time and nobody noticed:

- Fix omap3 off mode pull defines
- Allow multiple pdata quirks instead of just one
- Fix am335x and dm814x scm syscon to probe children too
- Fix compatible for ti81xx to allow use with 8250_omap as well
- Fix 8250_omap on omap5 by adding HWMOD_SWSUP_SIDLE_ACT flag
- Fix SoC detection for omap36/37 SoCs

* tag 'omap-for-v4.11/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP3: Fix SoC detection of OMAP36/37 Family
  ARM: OMAP5: Add HWMOD_SWSUP_SIDLE_ACT flag for UART
  ARM: dts: Fix compatible for ti81xx uarts for 8250
  ARM: dts: Fix am335x and dm814x scm syscon to probe children
  ARM: OMAP2+: Fix init for multiple quirks for the same SoC
  ARM: dts: Fix omap3 off mode pull defines

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 17:14:43 -08:00
Rafał Miłecki
40be0dda07 net: add devm version of alloc_etherdev_mqs function
This patch adds devm_alloc_etherdev_mqs function and devm_alloc_etherdev
macro. These can be used for simpler netdev allocation without having to
care about calling free_netdev.

Thanks to this change drivers, their error paths and removal paths may
get simpler by a bit.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-01-29 19:24:12 -05:00
Yuchung Cheng
7e98102f48 tcp: record pkts sent and retransmistted
Add two stats in SCM_TIMESTAMPING_OPT_STATS:

TCP_NLA_DATA_SEGS_OUT: total data packets sent including retransmission
TCP_NLA_TOTAL_RETRANS: total data packets retransmitted

The names are picked to be consistent with corresponding fields in
TCP_INFO. This allows applications that are using the timestamping
API to measure latency stats to also retrive retransmission rate
of application write.

Signed-off-by: Yuchung Cheng <ycheng@google.com>
Signed-off-by: Soheil Hassas Yeganeh <soheil@google.com>
Acked-by: Neal Cardwell <ncardwell@google.com>
Acked-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-01-29 19:17:23 -05:00
Olof Johansson
1ae7776189 Qualcomm ARM Based Driver Updates for v4.11
* Fix issues with SCM compile testing
 * Add SCM set remote state API
 * Mask APQ8064 SCM clock dependency issue
 * Add Qualcomm DMA folder to MAINTAINERS
 * Fix EBI2 dependencies
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYhigsAAoJEFKiBbHx2RXVHtcP/jcF1VmTbEytfV2XXVV5AuMx
 /wif9bR4HTrw2rR6WFmjJr0fTTteItpuc+KHge92WHteAvNlB5N1JmXqP9oMZu5c
 J5xMwbRv/0v46kTKH0ddmHNRPU6dM+YGTAvU4ELx6TDtaZLnfT42P0J237fmSLxI
 5omiuowu3oyx+EsLUT3BBLzYrjaW6iZinY3XF5PdfCh35YNxLqk1VmMPmJFJPNVb
 QlD2a57/4pthV6xCNVOrxVtXYpv1TAuErkKKlZmcbSJ1YRe1ZlIE3oBKJpGYEHw4
 gQGf/HnJP86gxjCit5IvA9GA5AfM29qvt1SmP/8ahTvEODXH+liR45E9fp2Xc1f5
 hmCyl+Qald6aek0ivxW8k3BBueSeIIlqBs2hUZBs4YwbBLr7jztLSclz8Sg37GNN
 Mwwi5ru3RzO8lyhnrtZB+gcXjRIxeuXu4JLV6E6jz4FntMqBVOEkQ0Ptss7Le/tG
 GkrQUDa+W7Zl7fPp90zQBRGxTqq/5qEpVjn9OgdkcWRRr1Pyvx+kiTKSpmnga5P1
 VxWXUWVWBP+8hN2Y6PePGw5HOPQy76CoW8yXrG8Syu+plWXqvN+arhAcJKpDFIsg
 49GJvbhjYYTuz0TQm5CB8gCCk7sw+Yqp0g2BPnKu3ghSgSRtI4l5umtd3HmuWuBj
 lIimN7WD6NEiAqjhaOxN
 =E4FV
 -----END PGP SIGNATURE-----

Merge tag 'qcom-drivers-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers

Qualcomm ARM Based Driver Updates for v4.11

* Fix issues with SCM compile testing
* Add SCM set remote state API
* Mask APQ8064 SCM clock dependency issue
* Add Qualcomm DMA folder to MAINTAINERS
* Fix EBI2 dependencies

* tag 'qcom-drivers-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  firmware: qcom_scm: Add set remote state API
  MAINTAINERS: Update the files to include the Qualcomm DMA folder
  bus: qcom_ebi2: default y if ARCH_QCOM
  firmware: qcom: scm: Mask APQ8064 core clk dependency
  firmware: qcom: scm: Add empty functions to help compile testing

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 16:08:07 -08:00
Vivien Didelot
f123f2fbed net: dsa: pass bridge device when a port leaves
Upon reception of the NETDEV_CHANGEUPPER, a leaving port is already
unbridged, so reflect this by assigning the port's bridge_dev pointer to
NULL before calling the port_bridge_leave DSA driver operation.

Now that the bridge_dev pointer is exposed to the drivers, reflecting
the current state of the DSA switch fabric is necessary for the drivers
to adjust their port based VLANs correctly.

Pass the bridge device pointer to the port_bridge_leave operation so
that drivers have all information to re-program their chips properly,
and do not need to cache it anymore.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-01-29 18:42:46 -05:00
Vivien Didelot
a5e9a02e1f net: dsa: move bridge device in dsa_port
Move the bridge_dev pointer from dsa_slave_priv to dsa_port so that DSA
drivers can access this information and remove the need to cache it.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-01-29 18:42:46 -05:00
Vivien Didelot
818be8489d net: dsa: add ds and index to dsa_port
Add the physical switch instance and port index a DSA port belongs to to
the dsa_port structure.

That can be used later to retrieve information about a physical port
when configuring a switch fabric, or lighten up struct dsa_slave_priv.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-01-29 18:42:46 -05:00
Vivien Didelot
a0c02161ec net: dsa: variable number of ports
Change the ports[DSA_MAX_PORTS] array of the dsa_switch structure for a
zero-length array, allocated at the same time as the dsa_switch
structure itself. A dsa_switch_alloc() helper is provided for that.

This commit brings no functional change yet since we pass DSA_MAX_PORTS
as the number of ports for the moment. Future patches can update the DSA
drivers separately to support dynamic number of ports.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-01-29 18:42:46 -05:00
Eric Dumazet
f1712c7371 can: Fix kernel panic at security_sock_rcv_skb
Zhang Yanmin reported crashes [1] and provided a patch adding a
synchronize_rcu() call in can_rx_unregister()

The main problem seems that the sockets themselves are not RCU
protected.

If CAN uses RCU for delivery, then sockets should be freed only after
one RCU grace period.

Recent kernels could use sock_set_flag(sk, SOCK_RCU_FREE), but let's
ease stable backports with the following fix instead.

[1]
BUG: unable to handle kernel NULL pointer dereference at (null)
IP: [<ffffffff81495e25>] selinux_socket_sock_rcv_skb+0x65/0x2a0

Call Trace:
 <IRQ>
 [<ffffffff81485d8c>] security_sock_rcv_skb+0x4c/0x60
 [<ffffffff81d55771>] sk_filter+0x41/0x210
 [<ffffffff81d12913>] sock_queue_rcv_skb+0x53/0x3a0
 [<ffffffff81f0a2b3>] raw_rcv+0x2a3/0x3c0
 [<ffffffff81f06eab>] can_rcv_filter+0x12b/0x370
 [<ffffffff81f07af9>] can_receive+0xd9/0x120
 [<ffffffff81f07beb>] can_rcv+0xab/0x100
 [<ffffffff81d362ac>] __netif_receive_skb_core+0xd8c/0x11f0
 [<ffffffff81d36734>] __netif_receive_skb+0x24/0xb0
 [<ffffffff81d37f67>] process_backlog+0x127/0x280
 [<ffffffff81d36f7b>] net_rx_action+0x33b/0x4f0
 [<ffffffff810c88d4>] __do_softirq+0x184/0x440
 [<ffffffff81f9e86c>] do_softirq_own_stack+0x1c/0x30
 <EOI>
 [<ffffffff810c76fb>] do_softirq.part.18+0x3b/0x40
 [<ffffffff810c8bed>] do_softirq+0x1d/0x20
 [<ffffffff81d30085>] netif_rx_ni+0xe5/0x110
 [<ffffffff8199cc87>] slcan_receive_buf+0x507/0x520
 [<ffffffff8167ef7c>] flush_to_ldisc+0x21c/0x230
 [<ffffffff810e3baf>] process_one_work+0x24f/0x670
 [<ffffffff810e44ed>] worker_thread+0x9d/0x6f0
 [<ffffffff810e4450>] ? rescuer_thread+0x480/0x480
 [<ffffffff810ebafc>] kthread+0x12c/0x150
 [<ffffffff81f9ccef>] ret_from_fork+0x3f/0x70

Reported-by: Zhang Yanmin <yanmin.zhang@intel.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Acked-by: Oliver Hartkopp <socketcan@hartkopp.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-01-29 18:30:56 -05:00
Olof Johansson
61c5e4927b Some extensions to the power-domain driver to support domains in
hiword registers (write-mask in upper 16bit) and domain-definitions
 for the rk3328 soc.
 
 Secondly a "driver" that attaches to the already existing grf nodes
 and is able to set static defaults for settings that cannot really
 be attached to any specific subsystem.
 Most GRF settings can already be set from drivers using them, but there
 are some behavioural settings like the mmc/jtag switch that cannot.
 
 As the commit message states this is really meant as a last line
 of defence for things that neither belong to a subsystem nor to the
 
 Having this here allows arm64 socs to have this as well and also
 moves another bit of code out of the arm32 mach-rockchip.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAliBTccQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgdMAB/42pPY0pKqOWlAfqzTSlIh98vi9jp0nZUu+
 6RMlaqewhHq/zbH0qqJdcBrYRZF+EmJpTDGG2nltNi8FLNMyr+y7a0FVyjk/u43L
 FnYELcDm7yeCZ0012ZP/4hlhWI9YizojbIKH4p2o8nIj64CS132ZMVVgojyzvVc1
 0WLWUf8FBiMqsBpa6Kl117pvKayagk79PM570Ee2kRBxanN8yQaKmXTqG670eKzo
 7nar1VGAubAVpCZfbv4opugGfrjYPJFX4gcu3yJvtRRN+hTt6idRP40YoCMZSVds
 +okL0XW4G70ioXqZBS59Wq5FJS7frr8HRJbYD8lZg2vF948ZQnbC
 =4aXM
 -----END PGP SIGNATURE-----

Merge tag 'v4.11-armsoc-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers

Some extensions to the power-domain driver to support domains in
hiword registers (write-mask in upper 16bit) and domain-definitions
for the rk3328 soc.

Secondly a "driver" that attaches to the already existing grf nodes
and is able to set static defaults for settings that cannot really
be attached to any specific subsystem.
Most GRF settings can already be set from drivers using them, but there
are some behavioural settings like the mmc/jtag switch that cannot.

As the commit message states this is really meant as a last line
of defence for things that neither belong to a subsystem nor to the

Having this here allows arm64 socs to have this as well and also
moves another bit of code out of the arm32 mach-rockchip.

* tag 'v4.11-armsoc-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: rockchip: drop rk3288 jtag/mmc switch handling
  soc: rockchip: add driver handling grf setup
  dt-bindings: add used but undocumented rockchip grf compatible values
  soc: rockchip: power-domain: add power domain support for rk3328
  dt-bindings: add binding for rk3328 power domains
  dt-bindings: power: add RK3328 SoCs header for idle-request
  soc: rockchip: power-domain: Support domain control in hiword-registers

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 14:32:07 -08:00
Olof Johansson
ef73594a38 Improvements for Exynos PMU driver for v4.11:
Beside basic function of setting proper configuration for low power modes, the
 Exynos PMU (Power Management Unit) driver is also a provider of syscon regmap
 for its registers.  This regmap is essential to many other drivers wanting to
 or needing to implement low power mode.
 
 Exynos pinctrl driver, before getting support for Runtime Power Management,
 needs access to this syscon regmap.  Let's do it in a DT ABI friendly way.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYglMqAAoJEME3ZuaGi4PXM44QAIwQYe+ZaLJojKgAJ2wIP0Mc
 0Jc7DrI7YGc5SQRpyOWztVEPuUH04tqCymYpAIqJ8UwsVGYERPglVQdVML+P9oyR
 syIP7COQy5KvDtKMOrMid2+KJjf6zcEHQFecFEEkqffTmtlwnfmpSrSbtoIHFoK4
 33vuikSP3npGh9rHOClXi+SMtvor1hYg/8hPD6zfeXIbt6D5zIzTW/dIAFDm1gbV
 xdVJusWLOPcdOBB7eTO5GxBjTCWcrOojJOXr1M3hR/46Z2Vv/WEPaLv4h/FhJxhQ
 tXBCBppKvrjsmGfnKiKwAHrFF999cAyfjAW7kpAF+hCtLIMR+R17TI+EJ4ahDrbf
 ZQH+otFq0YioQbhFh4HUJ6EImXSBaGdDOlT7HZLWlruj3Yc6vyiLL17qQcGZp63g
 wrot39P0v04jIJewr4OR72KnfIAfkEkHkxgZMwV/YibsuzwOxxP8leax4oh2UELg
 GrzkOdiEulRPyyY2Xlq1TIEQS3wFkYDJNQJ9INW1yp4NYgPx0Q2/5JPz2w9Ep8aO
 ONp3h//Rt4bJRqI3vyhhhU1Rj90sKfutewggHC4jycxHCkaBS6/xtw6HJfxZzC82
 QnDxK/2ylQVpbA1Hy8hP90HkdhsvhwcUsXmhH66EszyUmdhjgl+iPgtDJGKwcHEC
 SlnIwnmZqI0r6NFraoao
 =ZQ36
 -----END PGP SIGNATURE-----

Merge tag 'samsung-drivers-soc-pmu-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers

Improvements for Exynos PMU driver for v4.11:

Beside basic function of setting proper configuration for low power modes, the
Exynos PMU (Power Management Unit) driver is also a provider of syscon regmap
for its registers.  This regmap is essential to many other drivers wanting to
or needing to implement low power mode.

Exynos pinctrl driver, before getting support for Runtime Power Management,
needs access to this syscon regmap.  Let's do it in a DT ABI friendly way.

* tag 'samsung-drivers-soc-pmu-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  soc: samsung: pmu: Remove messages for failed memory allocation
  soc: samsung: pmu: Use of_device_get_match_data helper
  soc: samsung: pmu: Provide global function to get PMU regmap

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 14:30:31 -08:00