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147,665 commits

Author SHA1 Message Date
Nicolas Dichtel
7e6e1b5716 rtnetlink: advertise allmulti counter
Like what was done with IFLA_PROMISCUITY, add IFLA_ALLMULTI to advertise
the allmulti counter.
The flag IFF_ALLMULTI is advertised only if it was directly set by a
userland app.

Signed-off-by: Nicolas Dichtel <nicolas.dichtel@6wind.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-09-16 09:28:44 +01:00
Xinlei Lee
b404cb4599 soc: mediatek: Add mmsys func to adapt to dpi output for MT8186
Add mmsys func to manipulate dpi output format config for MT8186.

Co-developed-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: Nís F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/all/1663161662-1598-2-git-send-email-xinlei.lee@mediatek.com/
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-15 23:50:28 +02:00
Arnd Bergmann
387969b7ab Arm FF-A firmware driver updates for v6.1
Small set of changes in preparation to add support for FF-A v1.1
 specification later. It mainly contains:
 
 1. Splitting up ffa_ops into different categories namely information,
    message and memory. It helps to make info and memory operations
    independent from ffa_device so thata generic memory management
    module can use it without specific ffa_dev.
 2. Adds support for querying FF-A features and use the same to detect
    the support for 64-bit operations.
 3. Adds v1.1 get_partition_info support and use the same to set up
    32-bit execution mode flag automatically.
 4. Adds pointer to the ffa_dev_ops in struct ffa_dev and drop
    ffa_dev_ops_get() which enables to drop ffa_ops in optee_ffa
    structure using ffa_dev->ops directly. Additionally ffa_dev_ops is
    renamed as ffa_ops.
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Merge tag 'ffa-updates-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers

Arm FF-A firmware driver updates for v6.1

Small set of changes in preparation to add support for FF-A v1.1
specification later. It mainly contains:

1. Splitting up ffa_ops into different categories namely information,
   message and memory. It helps to make info and memory operations
   independent from ffa_device so thata generic memory management
   module can use it without specific ffa_dev.
2. Adds support for querying FF-A features and use the same to detect
   the support for 64-bit operations.
3. Adds v1.1 get_partition_info support and use the same to set up
   32-bit execution mode flag automatically.
4. Adds pointer to the ffa_dev_ops in struct ffa_dev and drop
   ffa_dev_ops_get() which enables to drop ffa_ops in optee_ffa
   structure using ffa_dev->ops directly. Additionally ffa_dev_ops is
   renamed as ffa_ops.

* tag 'ffa-updates-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  firmware: arm_ffa: Split up ffa_ops into info, message and memory operations
  firmware: arm_ffa: Set up 32bit execution mode flag using partiion property
  firmware: arm_ffa: Add v1.1 get_partition_info support
  firmware: arm_ffa: Rename ffa_dev_ops as ffa_ops
  firmware: arm_ffa: Make memory apis ffa_device independent
  firmware: arm_ffa: Use FFA_FEATURES to detect if native versions are supported
  firmware: arm_ffa: Add support for querying FF-A features
  firmware: arm_ffa: Remove ffa_dev_ops_get()
  tee: optee: Drop ffa_ops in optee_ffa structure using ffa_dev->ops directly
  firmware: arm_ffa: Add pointer to the ffa_dev_ops in struct ffa_dev

Link: https://lore.kernel.org/r/20220913100612.2924643-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15 22:07:07 +02:00
Maxime Ripard
2539932534 clk: Introduce the clk_hw_get_rate_range function
Some clock providers are hand-crafting their clk_rate_request, and need
to figure out the current boundaries of their clk_hw to fill it
properly.

Let's create such a function for clock providers.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-24-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:25 -07:00
Maxime Ripard
262ca38f4b clk: Stop forwarding clk_rate_requests to the parent
If the clock cannot modify its rate and has CLK_SET_RATE_PARENT,
clk_mux_determine_rate_flags(), clk_core_round_rate_nolock() and a
number of drivers will forward the clk_rate_request to the parent clock.

clk_core_round_rate_nolock() will pass the pointer directly, which means
that we pass a clk_rate_request to the parent that has the rate,
min_rate and max_rate of the child, and the best_parent_rate and
best_parent_hw fields will be relative to the child as well, so will
point to our current clock and its rate. The most common case for
CLK_SET_RATE_PARENT is that the child and parent clock rates will be
equal, so the rate field isn't a worry, but the other fields are.

Similarly, if the parent clock driver ever modifies the best_parent_rate
or best_parent_hw, this will be applied to the child once the call to
clk_core_round_rate_nolock() is done. best_parent_hw is probably not
going to be a valid parent, and best_parent_rate might lead to a parent
rate change different to the one that was initially computed.

clk_mux_determine_rate_flags() and the affected drivers will copy the
request before forwarding it to the parents, so they won't be affected
by the latter issue, but the former is still going to be there and will
lead to erroneous data and context being passed to the various clock
drivers in the same sub-tree.

Let's create two new functions, clk_core_forward_rate_req() and
clk_hw_forward_rate_request() for the framework and the clock providers
that will copy a request from a child clock and update the context to
match the parent's. We also update the relevant call sites in the
framework and drivers to use that new function.

Let's also add a test to make sure we avoid regressions there.

Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-22-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:11 -07:00
Maxime Ripard
22fb0e284f clk: Constify clk_has_parent()
clk_has_parent() doesn't modify the clocks being passed, so let's make
it const.

Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-21-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:32:06 -07:00
Maxime Ripard
c35e84b097 clk: Introduce clk_hw_init_rate_request()
clk-divider instantiates clk_rate_request internally for its round_rate
implementations to share the code with its determine_rate
implementations.

However, it's missing a few fields (min_rate, max_rate) that would be
initialized properly if it was using clk_core_init_rate_req().

Let's create the clk_hw_init_rate_request() function for clock providers
to be able to share the code to instation clk_rate_requests with the
framework. This will also be useful for some tests introduced in later
patches.

Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-17-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:31:40 -07:00
Maxime Ripard
f24a0b1c22 clk: Mention that .recalc_rate can return 0 on error
Multiple platforms (amlogic, imx8) return 0 when the clock rate cannot
be determined properly by the recalc_rate hook. Mention in the
documentation that the framework is ok with that.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220816112530.1837489-5-maxime@cerno.tech
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15 09:30:28 -07:00
Sebastian Andrzej Siewior
2747b93ebb locking: Detect includes rwlock.h outside of spinlock.h
From: Michael S. Tsirkin <mst@redhat.com>

The check for __LINUX_SPINLOCK_H within rwlock.h (and other files)
detects the direct include of the header file if it is at the very
beginning of the include section.
If it is listed later then chances are high that spinlock.h was already
included (including rwlock.h) and the additional listing of rwlock.h
will not cause any failure.

On PREEMPT_RT this additional rwlock.h will lead to compile failures
since it uses a different rwlock implementation.

Add __LINUX_INSIDE_SPINLOCK_H to spinlock.h and check for this instead
of __LINUX_SPINLOCK_H to detect wrong includes. This will help detect
direct includes of rwlock.h with without PREEMPT_RT enabled.

[ bigeasy: add remaining __LINUX_SPINLOCK_H user and rewrite
  commit description. ]

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/YweemHxJx7O8rjBx@linutronix.de
2022-09-15 16:14:02 +02:00
Dave Airlie
d1e2d6b78f Merge tag 'drm-intel-next-2022-08-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 feature pull for v6.1:

Features and functionality:
- Early Meteorlake (MTL) enabling (José, Radhakrishna, Clint, Imre, Vandita, Ville, Jani)
- Support more HDMI pixel clock frequencies on DG2 (Clint)
- Sanity check PCI BARs (Piotr Piórkowski)
- Enable DC5 on DG2 (Anusha)
- DG2 DMC firmware version bump to v2.07 (Madhumitha)
- New ADL-S PCI ID (José)

Refactoring and cleanups:
- Add display sub-struct to struct drm_i915_private (Jani)
- Add initial runtime info to device info (Jani)
- Split out HDCP and backlight registers to separate files (Jani)

Fixes:
- Skip wm/ddb readout for disabled pipes (Ville)
- HDMI port timing quirk for GLK ECS Liva Q2 (Diego Santa Cruz)
- Fix bw init null pointer dereference (Łukasz Bartosik)
- Disable PPS power hook for DP AUX backlight (Jouni)
- Avoid warnings on registering multiple backlight devices (Arun)
- Fix dual-link DSI backlight and CABC ports for display 11+ (Jani)
- Fix Type-C PHY ownership programming in HDMI legacy mode (Imre)
- Fix unclaimed register access while loading PIPEDMC-C/D (Imre)
- Bump up CDCLK for DG2 (Stan)
- Prune modes that require HDMI 2.1 FRL (Ankit)
- Disable FBC when PSR1 is enabled in display 12-13 (Matt)
- Fix TGL+ HDMI transcoder clock and DDI BUF disable order (Imre)
- Disable PSR before disable pipe (José)
- Disable DMC handlers during firmware loading/disabling on display 12+ (Imre)
- Disable clock gating for PIPEDMC-A/B as a workaround (Imre)

Merges:
- Two drm-next backmerges (Rodrigo, Jani)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87k06rfaku.fsf@intel.com
2022-09-15 22:38:13 +10:00
Mikko Perttunen
cc99f95d49 dt-bindings: Add Host1x context stream IDs on Tegra234
Add defines for stream IDs used for Host1x context isolation
on Tegra234. The same stream IDs are used for both NISO0 and
NISO1 SMMUs since Host1x's stream ID protection tables don't
make a distinction between the two.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 14:05:42 +02:00
Sumit Gupta
b713442214 soc/tegra: cbb: Add CBB 1.0 driver for Tegra194
Adding driver to handle errors from Control Backbone (CBB) which are
generated due to illegal accesses. CBB 1.0 is used in Tegra194 SoCs.
When an error is reported from a NOC within CBB, the driver prints debug
information about failed transaction like Error Code, Error Description,
Master, Address, AXI ID, Cache, Protection, Security Group etc. It then
causes system crash using BUG_ON() or call WARN() based on whether the
error type is fatal or not.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 12:41:36 +02:00
Sumit Gupta
96765cc475 soc/tegra: Set ERD bit to mask inband errors
Add a function to set the ERD (Error Response Disable) bit in the
MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error
handler driver.

ERD bit allows masking of SError due to inband errors which are caused
by illegal register accesses through CBB. When the bit is set, interrupt
is used for reporting errors and magic code '0xdead2003' is returned.
This change is only required for Tegra194 SoC as the config is moved to
CBB register space for future SoC's. Also, remove unmapping the
apbmisc_base as it's required to get the base address for accessing the
misc register.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 12:30:11 +02:00
Dave Marchevsky
47e34cb74d bpf: Add verifier check for BPF_PTR_POISON retval and arg
BPF_PTR_POISON was added in commit c0a5a21c25 ("bpf: Allow storing
referenced kptr in map") to denote a bpf_func_proto btf_id which the
verifier will replace with a dynamically-determined btf_id at verification
time.

This patch adds verifier 'poison' functionality to BPF_PTR_POISON in
order to prepare for expanded use of the value to poison ret- and
arg-btf_id in ongoing work, namely rbtree and linked list patchsets
[0, 1]. Specifically, when the verifier checks helper calls, it assumes
that BPF_PTR_POISON'ed ret type will be replaced with a valid type before
- or in lieu of - the default ret_btf_id logic. Similarly for arg btf_id.

If poisoned btf_id reaches default handling block for either, consider
this a verifier internal error and fail verification. Otherwise a helper
w/ poisoned btf_id but no verifier logic replacing the type will cause a
crash as the invalid pointer is dereferenced.

Also move BPF_PTR_POISON to existing include/linux/posion.h header and
remove unnecessary shift.

  [0]: lore.kernel.org/bpf/20220830172759.4069786-1-davemarchevsky@fb.com
  [1]: lore.kernel.org/bpf/20220904204145.3089-1-memxor@gmail.com

Signed-off-by: Dave Marchevsky <davemarchevsky@fb.com>
Acked-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
Link: https://lore.kernel.org/r/20220912154544.1398199-1-davemarchevsky@fb.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2022-09-15 02:44:07 -07:00
Mark Brown
12e51866c7
ASoC/qcom/arm64: Qualcomm ADSP DTS and binding fixes
Merge series from Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>:

Hi,

Dependencies/merging
====================
1. The DTS patches are independent.
2. The binding patches should come together, because of context changes. Could
   be one of: Qualcomm SoC, ASoC or DT tree.

Changes since v3
================
1. Patch 9-10: re-order, so first apr.yaml is corrected and then we convert to
   DT schema. This makes patchset fully bisectable in expense of changing the same
   lines twice.
2. Patch 11: New patch.

Changes since v2
================
1. Patch 9: rename and extend commit msg.
2. Add Rb tags.

Changes since v1
================
1. Patch 9: New patch.
2. Patch 10: Correct also sound/qcom,q6apm-dai.yaml (Rob).
2. Patch 13: New patch.
3. Add Rb/Tb tags.

Best regards,
Krzysztof

Krzysztof Kozlowski (15):
  arm64: dts: qcom: sdm630: align APR services node names with dtschema
  arm64: dts: qcom: sdm845: align APR services node names with dtschema
  arm64: dts: qcom: sm8250: align APR services node names with dtschema
  arm64: dts: qcom: msm8996: fix APR services nodes
  arm64: dts: qcom: sdm845: align dai node names with dtschema
  arm64: dts: qcom: msm8996: align dai node names with dtschema
  arm64: dts: qcom: qrb5165-rb5: align dai node names with dtschema
  arm64: dts: qcom: sm8250: use generic name for LPASS clock controller
  dt-bindings: soc: qcom: apr: correct service children
  ASoC: dt-bindings: qcom,q6asm: convert to dtschema
  ASoC: dt-bindings: qcom,q6adm: convert to dtschema
  ASoC: dt-bindings: qcom,q6dsp-lpass-ports: cleanup example
  ASoC: dt-bindings: qcom,q6dsp-lpass-clocks: cleanup example
  ASoC: dt-bindings: qcom,q6apm-dai: adjust indentation in example
  dt-bindings: soc: qcom: apr: add missing properties

 .../bindings/soc/qcom/qcom,apr.yaml           | 112 ++++++++++++++++--
 .../bindings/sound/qcom,q6adm-routing.yaml    |  52 ++++++++
 .../devicetree/bindings/sound/qcom,q6adm.txt  |  39 ------
 .../bindings/sound/qcom,q6apm-dai.yaml        |  21 ++--
 .../bindings/sound/qcom,q6asm-dais.yaml       | 112 ++++++++++++++++++
 .../devicetree/bindings/sound/qcom,q6asm.txt  |  70 -----------
 .../sound/qcom,q6dsp-lpass-clocks.yaml        |  36 +++---
 .../sound/qcom,q6dsp-lpass-ports.yaml         |  64 +++++-----
 arch/arm64/boot/dts/qcom/msm8996.dtsi         |  10 +-
 arch/arm64/boot/dts/qcom/qrb5165-rb5.dts      |   4 +-
 arch/arm64/boot/dts/qcom/sdm630.dtsi          |   8 +-
 arch/arm64/boot/dts/qcom/sdm845-db845c.dts    |   2 +-
 .../boot/dts/qcom/sdm845-xiaomi-beryllium.dts |   2 +-
 .../boot/dts/qcom/sdm845-xiaomi-polaris.dts   |   4 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |   8 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi          |  10 +-
 16 files changed, 346 insertions(+), 208 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6adm-routing.yaml
 delete mode 100644 Documentation/devicetree/bindings/sound/qcom,q6adm.txt
 create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6asm-dais.yaml
 delete mode 100644 Documentation/devicetree/bindings/sound/qcom,q6asm.txt

--
2.34.1
2022-09-15 10:29:01 +01:00
William Breathitt Gray
85ebe0afd3 isa: Introduce the module_isa_driver_with_irq helper macro
Several ISA drivers feature IRQ support that can configured via an "irq"
array module parameter. This array typically matches directly with the
respective "base" array module parameter. To reduce code repetition, a
module_isa_driver_with_irq helper macro is introduced to provide a check
ensuring that the number of "irq" passed to the module matches with the
respective number of "base".

Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Acked-by: William Breathitt Gray <william.gray@linaro.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
2022-09-15 10:28:18 +02:00
Oliver Hartkopp
626332696d can: raw: add CAN XL support
Enable CAN_RAW sockets to read and write CAN XL frames analogue to the
CAN FD extension (new CAN_RAW_XL_FRAMES sockopt).

A CAN XL network interface is capable to handle Classical CAN, CAN FD and
CAN XL frames. When CAN_RAW_XL_FRAMES is enabled, the CAN_RAW socket checks
whether the addressed CAN network interface is capable to handle the
provided CAN frame.

In opposite to the fixed number of bytes for
- CAN frames (CAN_MTU = sizeof(struct can_frame))
- CAN FD frames (CANFD_MTU = sizeof(struct can_frame))
the number of bytes when reading/writing CAN XL frames depends on the
number of data bytes. For efficiency reasons the length of the struct
canxl_frame is truncated to the needed size for read/write operations.
This leads to a calculated size of CANXL_HDR_SIZE + canxl_frame::len which
is enforced on write() operations and guaranteed on read() operations.

NB: Valid length values are 1 .. 2048 (CANXL_MIN_DLEN .. CANXL_MAX_DLEN).

Acked-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Link: https://lore.kernel.org/all/20220912170725.120748-8-socketcan@hartkopp.net
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-09-15 09:08:09 +02:00
Oliver Hartkopp
ebf87fc728 can: dev: add CAN XL support to virtual CAN
Make use of new can_skb_get_data_len() helper.
Add support for variable CANXL MTU using the new can_is_canxl_dev_mtu().

Acked-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Link: https://lore.kernel.org/all/20220912170725.120748-7-socketcan@hartkopp.net
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-09-15 09:08:09 +02:00
Oliver Hartkopp
fb08cba12b can: canxl: update CAN infrastructure for CAN XL frames
- add new ETH_P_CANXL ethernet protocol type
- update skb checks for CAN XL
- add alloc_canxl_skb() which now needs a data length parameter
- introduce init_can_skb_reserve() to reduce code duplication

Acked-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Link: https://lore.kernel.org/all/20220912170725.120748-6-socketcan@hartkopp.net
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-09-15 09:08:09 +02:00
Oliver Hartkopp
1a3e3034c0 can: canxl: introduce CAN XL data structure
This patch adds defines for data structures and length information for
CAN XL (CAN with eXtended data Length) which can transfer up to 2048
byte inside a single frame.

Notable changes from CAN FD:

- the 11 bit arbitration field is now named 'priority' instead of 'can_id'
  (there are no 29 bit identifiers nor RTR frames anymore)
- the data length needs a uint16 value to cover up to 2048 byte
  (the length element position is different to struct can[fd]_frame)
- new fields (SDT, AF) and a SEC bit have been introduced
- the virtual CAN interface identifier is not part if the CAN XL frame
  struct as this VCID value is stored in struct skbuff (analog to vlan id)

Acked-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Link: https://lore.kernel.org/all/20220912170725.120748-5-socketcan@hartkopp.net
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-09-15 09:08:09 +02:00
Oliver Hartkopp
061834624c can: set CANFD_FDF flag in all CAN FD frame structures
To simplify the testing in user space all struct canfd_frame's provided by
the CAN subsystem of the Linux kernel now have the CANFD_FDF flag set in
canfd_frame::flags.

NB: Handcrafted ETH_P_CANFD frames introduced via PF_PACKET socket might
not set this bit correctly. During the check for sufficient headroom in
PF_PACKET sk_buffs the uninitialized CAN sk_buff data structures are filled.
In the case of a CAN FD frame the CANFD_FDF flag is set accordingly.

As the CAN frame content is already zero initialized in alloc_canfd_skb()
the obsolete initialization of cf->flags in the CTU CAN FD driver has been
removed as it would overwrite the already set CANFD_FDF flag.

Acked-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Link: https://lore.kernel.org/all/20220912170725.120748-4-socketcan@hartkopp.net
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-09-15 09:08:08 +02:00
Oliver Hartkopp
467ef4c7b9 can: skb: add skb CAN frame data length helpers
Add two helpers to retrieve the data length from CAN sk_buffs and prepare
the length information to be a uint16 value for the CAN XL support.

Acked-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Link: https://lore.kernel.org/all/20220912170725.120748-3-socketcan@hartkopp.net
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-09-15 09:08:08 +02:00
Oliver Hartkopp
96a7457a14 can: skb: unify skb CAN frame identification helpers
Replace open coded checks for sk_buffs containing Classical CAN and
CAN FD frame structures as a preparation for CAN XL support.

With the added length check the unintended processing of CAN XL frames
having the CANXL_XLF bit set can be suppressed even when the skb->len
fits to non CAN XL frames.

The CAN_RAW socket needs a rework to use these helpers. Therefore the
use of these helpers is postponed to the CAN_RAW CAN XL integration.

The J1939 protocol gets a check for Classical CAN frames too.

Acked-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Link: https://lore.kernel.org/all/20220912170725.120748-2-socketcan@hartkopp.net
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-09-15 09:08:08 +02:00
Linus Walleij
94bc967b8d Samsung pinctrl drivers changes for v6.1
1. Minor fix in order of initializing pinctrl driver - GPIOs should be
    configured before registering gpiolib.
 2. Final steps to deprecated bindings headers with register constants.
    The constants were moved to include files in DTS directories, because
    these are not suitable for bindings.  Remove final references and
    mark binding header as deprecated to warn any users.
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Merge tag 'samsung-pinctrl-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

Samsung pinctrl drivers changes for v6.1

1. Minor fix in order of initializing pinctrl driver - GPIOs should be
   configured before registering gpiolib.
2. Final steps to deprecated bindings headers with register constants.
   The constants were moved to include files in DTS directories, because
   these are not suitable for bindings.  Remove final references and
   mark binding header as deprecated to warn any users.
2022-09-14 14:28:47 +02:00
Maxime Ripard
3f1a3a28e9 Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86
Tag (immutable branch) with v6.0-rc1 + the (acpi/x86) backlight
 detect refactor work. For merging into the acpi, drm-* and pdx86
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Merge tag 'backlight-detect-refactor-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86 into drm-misc-next

Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86

Tag (immutable branch) with v6.0-rc1 + the (acpi/x86) backlight
detect refactor work. For merging into the acpi, drm-* and pdx86
subsystems.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>

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# gpg: Signature made Mon 05 Sep 2022 09:25:44 AM IST
# gpg:                using RSA key BAF03B5D2718411A5E9E177E92EC4779440327DC
# gpg:                issuer "hdegoede@redhat.com"
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From: Hans de Goede <hdegoede@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/261afe3d-7790-e945-adf6-a2c96c9b1eff@redhat.com
2022-09-14 12:27:10 +01:00
Maxime Ripard
a108772d03
Merge drm/drm-next into drm-misc-next
We need 6.0-rc1 to merge the backlight rework PR.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2022-09-14 12:22:18 +01:00
Heiner Kallweit
1dd611a9c5 mmc: core: Switch to basic workqueue API for sdio_irq_work
The delay parameter isn't set by any user, therefore simplify the code
and switch to the basic workqueue API w/o delay support. This also
reduces the size of struct mmc_host.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://lore.kernel.org/r/13d8200a-e2a8-d907-38ce-a16fc5ce14aa@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2022-09-14 11:53:47 +02:00
Linus Torvalds
3245cb65fd Devicetree fixes for v6.0, take 2:
- Update some stale binding maintainer emails
 
 - Fix property name error in apple,aic binding
 
 - Add missing param to of_dma_configure_id() stub
 
 - Fix an off-by-one error in unflatten_dt_nodes()
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Merge tag 'devicetree-fixes-for-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree fixes from Rob Herring:

 - Update some stale binding maintainer emails

 - Fix property name error in apple,aic binding

 - Add missing param to of_dma_configure_id() stub

 - Fix an off-by-one error in unflatten_dt_nodes()

* tag 'devicetree-fixes-for-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  dt-bindings: pinctrl: qcom: drop non-working codeaurora.org emails
  dt-bindings: power: qcom,rpmpd: drop non-working codeaurora.org emails
  dt-bindings: apple,aic: Fix required item "apple,fiq-index" in affinity description
  dt-bindings: interconnect: fsl,imx8m-noc: drop Leonard Crestez
  of/device: Fix up of_dma_configure_id() stub
  MAINTAINERS: Update email of Neil Armstrong
  of: fdt: fix off-by-one error in unflatten_dt_nodes()
2022-09-14 10:22:39 +01:00
Conor Dooley
b4b025246c dt-bindings: clk: add PolarFire SoC fabric clock ids
Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs.
The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering
these clocks. For more information on the CCC hardware, see the
"PolarFire SoC FPGA Clocking Resources" document at the link below.

Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com
2022-09-14 10:57:07 +03:00
Conor Dooley
b56bae2dd6 clk: microchip: mpfs: add reset controller
Add a reset controller to PolarFire SoC's clock driver. This reset
controller is registered as an aux device and read/write functions
exported to the drivers namespace so that the reset controller can
access the peripheral device reset register.

Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com
2022-09-14 10:55:17 +03:00
Konrad Dybcio
2d48e6ea30 dt-bindings: power: rpmpd: Add SM6375 power domains
Add the bindings for SM6375 RPMPDs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220716193201.455728-1-konrad.dybcio@somainline.org
2022-09-13 22:25:35 -05:00
Stephan Gerhold
c40668048f dt-bindings: clock: Add schema for MSM8909 GCC
The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks,
resets and power domains for the various hardware blocks in the SoC.
Add a DT schema to describe it, similar to other Qualcomm SoCs.

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220706134132.3623415-2-stephan.gerhold@kernkonzept.com
2022-09-13 22:07:25 -05:00
Richard Acayan
657e932665 dt-bindings: clock: gcc-sdm845: add sdm670 global clocks
The Snapdragon 670 clocks will be added into the sdm845 gcc driver. Most
of the new clocks, GDSCs, and resets already have reserved IDs but there
are some resources that don't. Add the new clock from Snapdragon 670 and
document the differences between the SoC parent clocks.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220914013922.198778-2-mailingradian@gmail.com
2022-09-13 21:20:33 -05:00
Mark Brown
ca9b8f0486
MediaTek Helio X10 MT6795 - MT6331/6332 Regulators
Merge series from AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>:

In an effort to give some love to the apparently forgotten MT6795 SoC,
I am upstreaming more components that are necessary to support platforms
powered by this one apart from a simple boot to serial console.

This series adds support for the regulators found in MT6331 and MT6332
main/companion PMICs.

Adding support to each driver in each subsystem is done in different
patch series as to avoid spamming uninteresting patches to maintainers.

Tested on a MT6795 Sony Xperia M5 (codename "Holly") smartphone.
2022-09-13 17:43:23 +01:00
Taniya Das
c9a406b42f dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280
Support external mclk to interface external MI2S clocks for SC7280.

Fixes: 4185b27b3b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-5-git-send-email-quic_c_skakit@quicinc.com
2022-09-13 09:57:24 -05:00
Taniya Das
42801e6185 dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for SC7280. Update reg property min/max items in YAML schema.

Fixes: 4185b27b3b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-4-git-send-email-quic_c_skakit@quicinc.com
2022-09-13 09:57:23 -05:00
Taniya Das
1c3f9df77a dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280
Support external mclk to interface external MI2S clocks for SC7280.

Fixes: 4185b27b3b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-5-git-send-email-quic_c_skakit@quicinc.com
2022-09-13 09:47:35 -05:00
Taniya Das
be9439df23 dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for SC7280. Update reg property min/max items in YAML schema.

Fixes: 4185b27b3b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-4-git-send-email-quic_c_skakit@quicinc.com
2022-09-13 09:47:35 -05:00
Mark Brown
e2741d9942 Linux 6.0-rc4
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ASoC: Merge tag 'v6.0-rc4' into asoc-6.1

Linux 6.0-rc4 so we can test on BeagleBone again.
2022-09-13 15:05:38 +01:00
AngeloGioacchino Del Regno
1cc5a52e87
regulator: Add driver for MT6332 PMIC regulators
Add a driver for the regulators found in the MT6332 PMICs,
including six buck and four LDO regulators.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220913123456.384513-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-13 15:04:58 +01:00
AngeloGioacchino Del Regno
6f7a71f804
regulator: Add driver for MT6331 PMIC regulators
Add a driver for the regulators found in the MT6331 PMIC.
This PMIC features six buck and 21 Low DropOut (LDO) regulators.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220913123456.384513-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-13 15:04:56 +01:00
Namhyung Kim
b4e12b2d70 perf: Kill __PERF_SAMPLE_CALLCHAIN_EARLY
There's no in-tree user anymore.  Let's get rid of it.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220908214104.3851807-3-namhyung@kernel.org
2022-09-13 15:03:23 +02:00
Jiangshan Yi
4b9d1bc791 Input: hp_sdc: fix spelling typo in comment
Fix spelling typo in comment.

Reported-by: k2ci <kernel-bot@kylinos.cn>
Signed-off-by: Jiangshan Yi <yijiangshan@kylinos.cn>
Signed-off-by: Helge Deller <deller@gmx.de>
2022-09-13 14:04:34 +02:00
Vignesh Raghavendra
1607e6f928 dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62A
Add pinctrl macros for AM62AX SoCs. These macro definitions are similar
to that of previous platforms, but adding new definitions to avoid any
naming confusions in the SoC dts files.

checkpatch insists the following error exists:
ERROR: Macros with complex values should be enclosed in parentheses

However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Devarsh Thakkar <devarsht@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220901141328.899100-4-vigneshr@ti.com
2022-09-13 15:58:16 +05:30
Vignesh Raghavendra
a3c5297741 dt-bindings: arm: ti: Rearrange IOPAD macros alphabetically
Rearrange SOC specific IOPAD macros alphabetically, so that its easier
to read. No functional change intended.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Devarsh Thakkar <devarsht@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220901141328.899100-2-vigneshr@ti.com
2022-09-13 15:58:05 +05:30
Linus Torvalds
e839a75601 hyperv-fixes for v6.0-rc6
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Merge tag 'hyperv-fixes-signed-20220912' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux

Pull hyperv fixes from Wei Liu:

 - Fix an error handling issue in DRM driver (Christophe JAILLET)

 - Fix some issues in framebuffer driver (Vitaly Kuznetsov)

 - Two typo fixes (Jason Wang, Shaomin Deng)

 - Drop unnecessary casting in kvp tool (Zhou Jie)

* tag 'hyperv-fixes-signed-20220912' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux:
  Drivers: hv: Never allocate anything besides framebuffer from framebuffer memory region
  Drivers: hv: Always reserve framebuffer region for Gen1 VMs
  PCI: Move PCI_VENDOR_ID_MICROSOFT/PCI_DEVICE_ID_HYPERV_VIDEO definitions to pci_ids.h
  tools: hv: kvp: remove unnecessary (void*) conversions
  Drivers: hv: remove duplicate word in a comment
  tools: hv: Remove an extraneous "the"
  drm/hyperv: Fix an error handling path in hyperv_vmbus_probe()
2022-09-12 18:33:55 -04:00
Bjorn Helgaas
e8bdc5ea48 PCI/PTM: Add pci_suspend_ptm() and pci_resume_ptm()
We disable PTM during suspend because that allows some Root Ports to enter
lower-power PM states, which means we also need to disable PTM for all
downstream devices.  Add pci_suspend_ptm() and pci_resume_ptm() for this
purpose.

pci_enable_ptm() and pci_disable_ptm() are for drivers to use to enable or
disable PTM.  They use dev->ptm_enabled to keep track of whether PTM should
be enabled.

pci_suspend_ptm() and pci_resume_ptm() are PCI core-internal functions to
temporarily disable PTM during suspend and (depending on dev->ptm_enabled)
re-enable PTM during resume.

Enable/disable/suspend/resume all use internal __pci_enable_ptm() and
__pci_disable_ptm() functions that only update the PTM Control register.
Outline:

  pci_enable_ptm(struct pci_dev *dev)
  {
     __pci_enable_ptm(dev);
     dev->ptm_enabled = 1;
     pci_ptm_info(dev);
  }

  pci_disable_ptm(struct pci_dev *dev)
  {
     if (dev->ptm_enabled) {
       __pci_disable_ptm(dev);
       dev->ptm_enabled = 0;
     }
  }

  pci_suspend_ptm(struct pci_dev *dev)
  {
     if (dev->ptm_enabled)
       __pci_disable_ptm(dev);
  }

  pci_resume_ptm(struct pci_dev *dev)
  {
     if (dev->ptm_enabled)
       __pci_enable_ptm(dev);
  }

Nothing currently calls pci_resume_ptm(); the suspend path saves the PTM
state before disabling PTM, so the PTM state restore in the resume path
implicitly re-enables it.  A future change will use pci_resume_ptm() to fix
some problems with this approach.

Link: https://lore.kernel.org/r/20220909202505.314195-5-helgaas@kernel.org
Tested-by: Rajvi Jingar <rajvi.jingar@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-09-12 15:29:37 -05:00
Bjorn Helgaas
a47126ec29 PCI/PTM: Cache PTM Capability offset
Cache the PTM Capability offset instead of searching for it every time we
enable/disable PTM or save/restore PTM state.  No functional change
intended.

Link: https://lore.kernel.org/r/20220909202505.314195-2-helgaas@kernel.org
Tested-by: Rajvi Jingar <rajvi.jingar@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-09-12 15:28:43 -05:00
Arnd Bergmann
2c12f88cef Samsung DTS ARM64 changes for v6.0
1. Add binding headers for several Exynos850 and ExynosAutov9 clocks.
 2. ExynosAutov9: Add FSYS clock controller nodes.
 3. ExynosAutov9: Document serial compatible (used in DTS).
 4. Exynos850: Add Audio, IS, MFC clock controllers. Add IOMMU nodes.
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Merge tag 'samsung-dt64-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM64 changes for v6.0

1. Add binding headers for several Exynos850 and ExynosAutov9 clocks.
2. ExynosAutov9: Add FSYS clock controller nodes.
3. ExynosAutov9: Document serial compatible (used in DTS).
4. Exynos850: Add Audio, IS, MFC clock controllers. Add IOMMU nodes.

* tag 'samsung-dt64-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  dt-bindings: serial: samsung: add exynosautov9-uart compatible
  arm64: dts: exynos: Add SysMMU nodes for Exynos850
  arm64: dts: exynos: Add CMU_AUD, CMU_IS and CMU_MFCMSCL for Exynos850
  arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
  dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
  dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
  dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
  dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
  dt-bindings: clock: exynosautov9: add fsys1 clock definitions
  dt-bindings: clock: exynosautov9: add fys0 clock definitions
  dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1

Link: https://lore.kernel.org/r/20220909150849.820523-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-12 17:19:57 +02:00
Arnd Bergmann
c3fe295c2e Powerdomain drivers for rv1126 and rk3588 socs, keep current state of
power-domains instead of always enabling when adding them, add rv1126
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Merge tag 'v6.1-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers

Powerdomain drivers for rv1126 and rk3588 socs, keep current state of
power-domains instead of always enabling when adding them, add rv1126
io domains and add binding for another "general register files" syscon.

* tag 'v6.1-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  soc: rockchip: power-domain: add power domain support for rk3588
  soc: rockchip: power-domain: do not enable domain when adding it
  dt-bindings: power: rockchip: Add bindings for rk3588
  dt-bindings: arm: rockchip: add rk5388 compatible string to pmu.yaml
  dt-bindings: power: add power-domain header for rk3588
  soc: rockchip: io-domain: Add RV1126 IO domains
  dt-bindings: power: rockchip: Document RV1126 PMU IO domains
  soc: rockchip: power-domain: Add RV1126 power domains
  dt-bindings: power: rockchip: Document RV1126 power-controller
  dt-bindings: power: Add power-domain header for RV1126
  dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf

Link: https://lore.kernel.org/r/2252399.ElGaqSPkdT@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-12 17:08:54 +02:00