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linux/drivers/clk/rockchip
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Sebastian Reichel bd588d5256 clk: rockchip: fix error for unknown clocks 
commit 12fd64baba upstream.

There is a clk == NULL check after the switch to check for
unsupported clk types. Since clk is re-assigned in a loop,
this check is useless right now for anything but the first
round. Let's fix this up by assigning clk = NULL in the
loop before the switch statement.

Fixes: a245fecbb8 ("clk: rockchip: add basic infrastructure for clock branches")
Cc: stable@vger.kernel.org
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
[added fixes + stable-cc]
Link: https://lore.kernel.org/r/20240325193609.237182-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
History 2024-10-10 11:57:54 +02:00
..
clk-cpu.c clk: rockchip: allow additional mux options for cpu-clock frequency changes 2022-11-14 15:34:18 +01:00
clk-ddr.c clk: rockchip: Export rockchip_clk_register_ddrclk() 2020-09-22 15:16:37 +02:00
clk-half-divider.c clk: rockchip: Demote non-conformant kernel-doc header in half-divider 2021-01-26 00:24:05 +01:00
clk-inverter.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-mmc-phase.c clk: rockchip: fix mmc get phase 2020-03-06 12:06:01 -08:00
clk-muxgrf.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 2019-06-05 17:36:37 +02:00
clk-pll.c clk: rockchip: Fix memory leak in rockchip_clk_register_pll() 2022-11-23 14:51:30 +01:00
clk-px30.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3036.c clk: rockchip: Add support for hclk_sfc on rk3036 2021-07-16 00:33:42 +02:00
clk-rk3128.c clk: rockchip: rk3128: Fix HCLK_OTG gate register 2024-01-20 11:51:42 +01:00
clk-rk3188.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3228.c clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 2024-10-04 16:29:26 +02:00
clk-rk3288.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3308.c clk: rockchip: make rk3308 ddrphy4x clock critical 2021-07-29 12:43:11 +02:00
clk-rk3328.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3368.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3399.c clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent 2023-03-07 11:26:27 +01:00
clk-rk3568.c clk: rockchip: rk3568: Add PLL rate for 292.5MHz 2024-01-20 11:51:42 +01:00
clk-rk3588.c clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p 2024-10-04 16:29:32 +02:00
clk-rv1108.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rv1126.c Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next 2023-08-30 14:38:19 -07:00
clk.c clk: rockchip: fix error for unknown clocks 2024-10-10 11:57:54 +02:00
clk.h clk: rockchip: add clock controller for the RK3588 2022-11-15 11:37:41 +01:00
Kconfig clk: rockchip: add clock controller for the RK3588 2022-11-15 11:37:41 +01:00
Makefile clk: rockchip: add clock controller for the RK3588 2022-11-15 11:37:41 +01:00
rst-rk3588.c clk: rockchip: add clock controller for the RK3588 2022-11-15 11:37:41 +01:00
softrst.c clk: rockchip: add lookup table support 2022-11-14 15:35:07 +01:00