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525ad89dd9
The NPU cores have their own access to the memory bus, and this isn't cache coherent with the CPUs. Add IOCTLs so userspace can mark when the caches need to be flushed, and also when a writer job needs to be waited for before the buffer can be accessed from the CPU. Initially based on the same IOCTLs from the Etnaviv driver. v2: - Don't break UABI by reordering the IOCTL IDs (Jeff Hugo) v3: - Check that padding fields in IOCTLs are zero (Jeff Hugo) v6: - Fix conversion logic to make sure we use DMA_BIDIRECTIONAL when needed (Lucas Stach) v8: - Always sync BOs in both directions (Robin Murphy) Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-5-77ebd484941e@tomeuvizoso.net |
History
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| .. | ||
| amdgpu_drm.h | ||
| amdxdna_accel.h | ||
| armada_drm.h | ||
| asahi_drm.h | ||
| drm.h | ||
| drm_fourcc.h | ||
| drm_mode.h | ||
| drm_sarea.h | ||
| etnaviv_drm.h | ||
| exynos_drm.h | ||
| habanalabs_accel.h | ||
| i915_drm.h | ||
| ivpu_accel.h | ||
| lima_drm.h | ||
| msm_drm.h | ||
| nouveau_drm.h | ||
| nova_drm.h | ||
| omap_drm.h | ||
| panfrost_drm.h | ||
| panthor_drm.h | ||
| pvr_drm.h | ||
| qaic_accel.h | ||
| qxl_drm.h | ||
| radeon_drm.h | ||
| rocket_accel.h | ||
| tegra_drm.h | ||
| v3d_drm.h | ||
| vc4_drm.h | ||
| vgem_drm.h | ||
| virtgpu_drm.h | ||
| vmwgfx_drm.h | ||
| xe_drm.h | ||