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90c448fef3
This patch adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in
AMDGPU_INFO_IOCTL to get the size and alignment of shadow
and csa objects from the FW setup. This information is
required for the userqueue consumers.
V2: Added Alex's suggestions and addressed review comments:
- make this query IP specific (GFX/SDMA etc)
- give a better title (AMDGPU_INFO_UQ_METADATA)
- restructured the code as per sample code shared by Alex
V3: Split the UAPI patch from shadow_size_fn modifications
V4: Addressed review comments from UAPI review (Marek/Pierre-Eric)
- Change the query name to AMDGPU_INFO_UQ_FW_AREAS
- remove unused inpur parameter for AMDGPU_HW_IP*
UAPI link: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/400/
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Arvind Yadav <arvind.yadav@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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History
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| .. | ||
| amdgpu_drm.h | ||
| amdxdna_accel.h | ||
| armada_drm.h | ||
| drm.h | ||
| drm_fourcc.h | ||
| drm_mode.h | ||
| drm_sarea.h | ||
| etnaviv_drm.h | ||
| exynos_drm.h | ||
| habanalabs_accel.h | ||
| i915_drm.h | ||
| ivpu_accel.h | ||
| lima_drm.h | ||
| msm_drm.h | ||
| nouveau_drm.h | ||
| omap_drm.h | ||
| panfrost_drm.h | ||
| panthor_drm.h | ||
| pvr_drm.h | ||
| qaic_accel.h | ||
| qxl_drm.h | ||
| radeon_drm.h | ||
| tegra_drm.h | ||
| v3d_drm.h | ||
| vc4_drm.h | ||
| vgem_drm.h | ||
| virtgpu_drm.h | ||
| vmwgfx_drm.h | ||
| xe_drm.h | ||