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The PCIe 3 PHY in the RK3588 requires a running external reference clock
for both external bus transfers and some internal PIPE operations.
Without this clock, the PCIe3 controller fails to initialize and ignores
DBI transactions indefinitely, which stalls the Linux boot process.
On most RK3588 boards, this is evidently not an issue. But on some "SoM"
designs (Turing RK1, Mixtile Core 3588E, ArmSoM AIM7, to name a few),
this clock is only provided when the CLKREQ# signal is asserted.
The PCIe 3 PHY generates the CLKREQ# signal when it knows it needs the
reference clock for proper operation. Unfortunately, the current DT for
Turing RK1 does not mux out these low-speed signals, resulting in broken
boots and potentially other issues.
This patch, following the previous one that split up the PCIe pinctrls,
resolves this problem for Turing RK1 by explicitly muxing all of the
signals needed for PCIe 2 and 3 support.
Cc: Jonathan Bennett <jbennett@incomsystems.biz>
Fixes:
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Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the reStructuredText markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.