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Maíra Canal 5654126207 drm/v3d: Address race-condition in MMU flush 
[ Upstream commit cf1becb7f9 ]

We must first flush the MMU cache and then, flush the TLB, not the other
way around. Currently, we can see a race condition between the MMU cache
and the TLB when running multiple rendering processes at the same time.
This is evidenced by MMU errors triggered by the IRQ.

Fix the MMU flush order by flushing the MMU cache and then the TLB.
Also, in order to address the race condition, wait for the MMU cache flush
to finish before starting the TLB flush.

Fixes: 57692c94dc ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+")
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240923141348.2422499-2-mcanal@igalia.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2024-12-09 10:32:00 +01:00
..
drm drm/v3d: Address race-condition in MMU flush 2024-12-09 10:32:00 +01:00
host1x gpu: host1x: Do not setup DMA for virtual devices 2024-05-17 12:02:15 +02:00
ipu-v3 drm for 6.6-rc1 2023-08-30 13:34:34 -07:00
trace gpu/trace: add a gpu total memory usage tracepoint 2020-03-03 17:52:41 -05:00
vga PCI/VGA: Move vgaarb to drivers/pci 2022-03-09 18:30:46 -06:00
Makefile gpu: host1x: Add context bus 2022-06-01 11:50:42 +02:00