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75d37750a7
In order to avoid having userspace to use MI_MEM_FENCE,
we are adding a mechanism for userspace to generate a
PCI memory barrier with low overhead (avoiding IOCTL call
as well as writing to VRAM will adds some overhead).
This is implemented by memory-mapping a page as uncached
that is backed by MMIO on the dGPU and thus allowing userspace
to do memory write to the page without invoking an IOCTL.
We are selecting the MMIO so that it is not accessible from
the PCI bus so that the MMIO writes themselves are ignored,
but the PCI memory barrier will still take action as the MMIO
filtering will happen after the memory barrier effect.
When we detect special defined offset in mmap(), We are mapping
4K page which contains the last of page of doorbell MMIO range
to userspace for same purpose.
For user to query special offset we are adding special flag in
mmap_offset ioctl which needs to be passed as follows,
struct drm_xe_gem_mmap_offset mmo = {
.handle = 0, /* this must be 0 */
.flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER,
};
igt_ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo);
map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo);
IGT :
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History
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| .. | ||
| amdgpu_drm.h | ||
| armada_drm.h | ||
| drm.h | ||
| drm_fourcc.h | ||
| drm_mode.h | ||
| drm_sarea.h | ||
| etnaviv_drm.h | ||
| exynos_drm.h | ||
| habanalabs_accel.h | ||
| i915_drm.h | ||
| ivpu_accel.h | ||
| lima_drm.h | ||
| msm_drm.h | ||
| nouveau_drm.h | ||
| omap_drm.h | ||
| panfrost_drm.h | ||
| panthor_drm.h | ||
| pvr_drm.h | ||
| qaic_accel.h | ||
| qxl_drm.h | ||
| radeon_drm.h | ||
| tegra_drm.h | ||
| v3d_drm.h | ||
| vc4_drm.h | ||
| vgem_drm.h | ||
| virtgpu_drm.h | ||
| vmwgfx_drm.h | ||
| xe_drm.h | ||