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The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI mode. The PLL manager framework doesn't pass the CRTC state to the PLL's enable hook, so prepare here for the conversion to use the PLL manager for Cx0 PHY PLLs by determining the DP/HDMI mode from the PLL state. For C10 PHYs use the fact that the HDMI divider value in the PLL registers are set if and only if the PLL is in HDMI mode. For C20 PHYs use the DP mode flag programmed to the VDR SERDES register, which is set if and only if the PLL is in DP mode. Assert that the above PLL/VDR SERDES register values match the DP/HDMI mode being configured already during state computation. This also allows dropping the is_dp param from the __intel_cx0pll_enable() function, since it can retrieve this now from the PLL state. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-12-mika.kahola@intel.com |
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Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the reStructuredText markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.