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Palmer Dabbelt 9347ce54cd RISC-V: __test_and_op_bit_ord should be strongly ordered 
I mis-read the documentation.  After looking at it again the
documentation is actually as clear as it can be, it's just that I didn't
actually read it in order and therefor did the wrong thing.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
History 2017-11-28 14:04:05 -08:00
..
asm RISC-V: __test_and_op_bit_ord should be strongly ordered 2017-11-28 14:04:05 -08:00
uapi/asm RISC-V: User-facing API 2017-09-26 15:26:48 -07:00