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9eb77e4207
* Add amlogic a1 SoC family PLL and peripheral clock controller support -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAmSDNMkACgkQ5vwPHDfy 2oWweg/8C9udSB8/Jd+T1fBNNv/+dTXCQPgMZmCaVep2i3Ci27wEjZMFCOWoM1Wc ZAG81adJXNqkQ9aAM6J9IQaMGx/4YDYTqg/SH+bYs+yPpZ7XjbDABjX4HbWDby2M CsslQwk25VcyEajTUxYDnGTuJ2Lab9ECk9o/qc2/Lq/t4sRp+EMO/Gtumg6Uu5Lb FPFTXtca4YsTOt3ZkvlDp9DCWspU89N3NYBRiyKGDhrgheWCTNEs34bWpDh6Wh1M DpWkFrpVQVOrwbs1jdoHMV5nyjgzp6r3Dpb/wYdhJMEFJvrBhv7geFJ6EhhOrWcD Wvd1lERt25hJSuxjaqVr/EA7l8l0lZeoGYLh1KXDbI56Zsb6HbMeCif/JxccNTO1 MIzVCqCBjL2/lN0MiAlH1ZnWABJ7qFK8uG0416m6XaTBQIiJZfXGhLQ14i0q9rBJ wQ+suP8+os8FZCZO4yvD3re5d8DL3HMKTj7ldrw2HdoKoEcBtawGc2yGGmz/Es+e Zbx8yd0IUQ+RVf6xZr607XSgZF31y3SAVSoilrDGoDBzNOCuuxNZ0ePUpoycRI3I qojnTmCntvFyWNxoByZQj0n6OR7lB9vd7PsQVQVAvL6d90ZFDTSX9YEhs2d8zHPo YBh4yssy5yXmkD8bYSG7UxDwihHPy7tMe7vMbnHVYchBUfHyMJQ= =1CjJ -----END PGP SIGNATURE----- Merge tag 'clk-meson-v6.5-1' of https://github.com/BayLibre/clk-meson into clk-allwinner Pull Amlogic clk driver updates from Jerome Brunet: - Add amlogic a1 SoC family PLL and peripheral clock controller support * tag 'clk-meson-v6.5-1' of https://github.com/BayLibre/clk-meson: clk: meson: a1: add Amlogic A1 Peripherals clock controller driver clk: meson: a1: add Amlogic A1 PLL clock controller driver clk: meson: introduce new pll power-on sequence for A1 SoC family clk: meson: make pll rst bit as optional dt-bindings: clock: meson: add A1 Peripherals clock controller bindings dt-bindings: clock: meson: add A1 PLL clock controller bindings |
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Linux kernel
============
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