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linux/arch/mips/include/asm/pgtable-bits.h
Paul Cercueil 95b1f6db67 MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA 
Previously, in cpu_probe_ingenic(), c->writecombine was set to
_CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when
CONFIG_MACH_INGENIC was set. This made it impossible to support multiple
CPUs.

Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA
directly and removing the dependency on CONFIG_MACH_INGENIC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:26:36 +02:00

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