linux/arch/xtensa/kernel
Max Filippov fd5507bac2 xtensa: fix secondary core boot in SMP
commit ab45fb1450 upstream.

There are multiple factors adding to the issue in different
configurations:

- commit 17290231df ("xtensa: add fixup for double exception raised
  in window overflow") added function window_overflow_restore_a0_fixup to
  double exception vector overlapping reset vector location of secondary
  processor cores.
- on MMUv2 cores RESET_VECTOR1_VADDR may point to uncached kernel memory
  making code overlapping depend on cache type and size, so that without
  cache or with WT cache reset vector code overwrites double exception
  code, making issue even harder to detect.
- on MMUv3 cores RESET_VECTOR1_VADDR may point to unmapped area, as
  MMUv3 cores change virtual address map to match MMUv2 layout, but
  reset vector virtual address is given for the original MMUv3 mapping.
- physical memory region of the secondary reset vector is not reserved
  in the physical memory map, and thus may be allocated and overwritten
  at arbitrary moment.

Fix it as follows:

- move window_overflow_restore_a0_fixup code to .text section.
- define RESET_VECTOR1_VADDR so that it points to reset vector in the
  cacheable MMUv2 map for cores with MMU.
- reserve reset vector region in the physical memory map. Drop separate
  literal section and build mxhead.S with text section literals.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Luis Henriques <luis.henriques@canonical.com>
History 2015-12-13 17:49:05 +00:00
..
.gitignore xtensa: tell git to ignore generated files 2013-06-05 10:14:19 -07:00
align.S xtensa: keep a3 and excsave1 on entry to exception handlers 2013-09-06 09:47:41 -07:00
asm-offsets.c xtensa: add support for TLS 2013-02-23 19:35:57 -08:00
coprocessor.S xtensa: keep a3 and excsave1 on entry to exception handlers 2013-09-06 09:47:41 -07:00
entry.S xtensa: fixes for configs without loop option 2015-12-13 17:49:02 +00:00
head.S xtensa: fixes for configs without loop option 2015-12-13 17:49:02 +00:00
irq.c xtensa: Use irq_set_affinity instead of homebrewn code 2014-03-04 17:37:55 +01:00
Makefile xtensa: fix secondary core boot in SMP 2015-12-13 17:49:05 +00:00
mcount.S xtensa: add static function tracer support 2013-07-08 01:18:57 -07:00
module.c xtensa: clean up files to make them code-style compliant 2012-12-18 21:10:25 -08:00
mxhead.S xtensa: add SMP support 2014-01-14 10:19:58 -08:00
pci-dma.c xtensa: fix address checks in dma_{alloc,free}_coherent 2014-10-05 13:40:56 -07:00
pci.c xtensa: fix section mismatch in pcibios_fixup_bus 2013-06-05 10:14:22 -07:00
platform.c xtensa: cleanup ccount frequency tracking 2013-07-08 01:11:37 -07:00
process.c xtensa: Use generic idle loop 2013-04-08 17:39:29 +02:00
ptrace.c xtensa: add support for TLS 2013-02-23 19:35:57 -08:00
setup.c xtensa: fix secondary core boot in SMP 2015-12-13 17:49:05 +00:00
signal.c xtensa: don't use alternate signal stack on threads 2013-10-15 13:39:16 -07:00
smp.c xtensa: optimize local_flush_tlb_kernel_range 2014-04-06 21:29:17 +04:00
stacktrace.c xtensa: provide custom CALLER_ADDR* implementations 2013-05-09 01:07:10 -07:00
syscall.c xtensa: avoid mmap cache aliasing 2013-02-23 19:12:53 -08:00
time.c xtensa: export ccount_freq 2014-01-19 20:00:48 +04:00
traps.c xtensa: implement CPU hotplug 2014-01-14 10:19:59 -08:00
vectors.S xtensa: fix secondary core boot in SMP 2015-12-13 17:49:05 +00:00
vmlinux.lds.S xtensa: fix secondary core boot in SMP 2015-12-13 17:49:05 +00:00
xtensa_ksyms.c xtensa: export __{invalidate,flush}_dcache_range 2014-04-02 01:35:50 +04:00