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linux/drivers/cxl/core
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Dan Williams a76b62518e cxl/port: Fix cxl_test register enumeration regression 
The cxl_test unit test environment models a CXL topology for
sysfs/user-ABI regression testing. It uses interface mocking via the
"--wrap=" linker option to redirect cxl_core routines that parse
hardware registers with versions that just publish objects, like
devm_cxl_enumerate_decoders().

Starting with:

Commit 19ab69a60e ("cxl/port: Store the port's Component Register mappings in struct cxl_port")

...port register enumeration is moved into devm_cxl_add_port(). This
conflicts with the "cxl_test avoids emulating registers stance" so
either the port code needs to be refactored (too violent), or modified
so that register enumeration is skipped on "fake" cxl_test ports
(annoying, but straightforward).

This conflict has happened previously and the "check for platform
device" workaround to avoid instrusive refactoring was deployed in those
scenarios. In general, refactoring should only benefit production code,
test code needs to remain minimally instrusive to the greatest extent
possible.

This was missed previously because it may sometimes just cause warning
messages to be emitted, but it can also cause test failures. The
backport to -stable is only nice to have for clean cxl_test runs.

Fixes: 19ab69a60e ("cxl/port: Store the port's Component Register mappings in struct cxl_port")
Cc: stable@vger.kernel.org
Reported-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Tested-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/169476525052.1013896.6235102957693675187.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
History 2023-09-22 14:28:42 -07:00
..
core.h Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
hdm.c Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
Makefile cxl/pci: Find and register CXL PMU devices 2023-05-30 11:20:35 -07:00
mbox.c cxl/mbox: Fix CEL logic for poison and security commands 2023-09-14 13:48:49 -07:00
memdev.c cxl/memdev: Only show sanitize sysfs files when supported 2023-07-28 13:16:54 -06:00
pci.c Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
pmem.c cxl/memdev: Formalize endpoint port linkage 2023-06-25 14:31:33 -07:00
pmu.c cxl/pci: Find and register CXL PMU devices 2023-05-30 11:20:35 -07:00
port.c cxl/port: Fix cxl_test register enumeration regression 2023-09-22 14:28:42 -07:00
region.c cxl/region: Refactor granularity select in cxl_port_setup_targets() 2023-09-14 20:47:42 -07:00
regs.c Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
suspend.c PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
trace.c cxl/trace: Add an HPA to cxl_poison trace events 2023-04-23 11:46:13 -07:00
trace.h cxl/memdev: Trace inject and clear poison as cxl_poison events 2023-04-23 12:08:39 -07:00