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Russ Anderson 2022c1f136 [IA64] Update Altix nofault code 
Montecito and Montvale behaves slightly differently than previous
Itanium processors, resulting in the MCA due to a failed PIO read
to sometimes surfacing outside the nofault code.  This code is
based on discussions with Intel CPU architects and verified at
customer sites.

Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
History 2008-01-03 13:22:54 -08:00
..
include [IA64-SGI] Older PROM WAR for device flush code 2006-01-17 10:08:37 -08:00
kernel [IA64] Update Altix nofault code 2008-01-03 13:22:54 -08:00
pci [IA64] Two trivial spelling fixes 2007-12-18 17:02:21 -08:00
Makefile [IA64-SGI] Recursive flags do not work for selective builds 2006-01-26 13:17:34 -08:00