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For correct cache coherency on some architectures, DMA buffers must be allocated in a different cache line than data that is concurrently used by the CPU. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Takashi Iwai <tiwai@suse.de>
308 lines
7.3 KiB
308 lines
7.3 KiB