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Thomas Gleixner 822ef687a0 x86/speculation/swapgs: Exclude ATOMs from speculation through SWAPGS ... commit f36cf386e3 upstream. Intel provided the following information: On all current Atom processors, instructions that use a segment register value (e.g. a load or store) will not speculatively execute before the last writer of that segment retires. Thus they will not use a speculatively written segment value. That means on ATOMs there is no speculation through SWAPGS, so the SWAPGS entry paths can be excluded from the extra LFENCE if PTI is disabled. Create a separate bug flag for the through SWAPGS speculation and mark all out-of-order ATOMs and AMD/HYGON CPUs as not affected. The in-order ATOMs are excluded from the whole mitigation mess anyway. Reported-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Tyler Hicks <tyhicks@canonical.com> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> [bwh: Backported to 3.16: - There's no whitelist entry (or any support) for Hygon CPUs - Use the next available X86_BUG number - Adjust context, indentation] Signed-off-by: Ben Hutchings <ben@decadent.org.uk>		History 2019-08-13 12:39:22 +01:00
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asm	x86/speculation/swapgs: Exclude ATOMs from speculation through SWAPGS	2019-08-13 12:39:22 +01:00
uapi/asm	x86/speculation/mds: Add basic bug infrastructure for MDS	2019-05-22 23:15:20 +01:00