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Heiko Stuebner 94085032b4 clk: rockchip: fix rk3066 pll lock bit location ... commit 12551f0239 upstream. The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll. The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table. Fix this by defining separate pll definitions for rk3066 with the correct locking indices. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Fixes: 2c14736c75 ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks") Tested-by: FUKAUMI Naoki <naobsd@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		History 2015-01-27 08:29:38 -08:00
..
clk-cpu.c	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
clk-pll.c	clk: rockchip: change pll rate without a clk-notifier	2014-09-27 17:57:04 +02:00
clk-rk3188.c	clk: rockchip: fix rk3066 pll lock bit location	2015-01-27 08:29:38 -08:00
clk-rk3288.c	clk: rockchip: fix rk3288 cpuclk core dividers	2015-01-27 08:29:38 -08:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	clk-divider: Fix READ_ONLY when divider > 1	2014-11-17 11:13:52 -08:00
clk.h	clk: rockchip: add restart handler	2014-10-01 14:11:42 +02:00
Makefile	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00