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linux/drivers/clk/pistachio
History
Kevin Cernekee 17bfa3f7b3 clk: pistachio: Add sanity checks on PLL configuration 
When setting the PLL rates, check that:

 - VCO is within range
 - PFD is within range
 - PLL is disabled when postdiv is changed
 - postdiv2 <= postdiv1

Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
History 2015-06-04 12:43:39 -07:00
..
clk-pistachio.c CLK: Pistachio: Register external clock gates 2015-03-31 11:59:31 +02:00
clk-pll.c clk: pistachio: Add sanity checks on PLL configuration 2015-06-04 12:43:39 -07:00
clk.c CLK: Add basic infrastructure for Pistachio clocks 2015-03-31 11:58:56 +02:00
clk.h CLK: Pistachio: Add PLL driver 2015-03-31 11:59:04 +02:00
Makefile CLK: Pistachio: Register core clocks 2015-03-31 11:59:10 +02:00