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linux/drivers/pinctrl/intel
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Andy Shevchenko 849f2d0665 pinctrl: intel: Set pin direction properly 
[ Upstream commit 17fab47369 ]

There are two bits in the PADCFG0 register to configure direction, one per
TX/RX buffers.

For now we wrongly assume that the GPIO is always requested before it is being
used, which is not true when the GPIO is used through irqchip. In this case the
GPIO is never requested and we never enable RX buffer for it.

Fix this by setting both bits accordingly.

Reported-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
History 2017-07-05 14:40:24 +02:00
..
Kconfig pinctrl: intel: Add Intel Merrifield pin controller support 2016-06-29 09:59:35 +02:00
Makefile pinctrl: intel: Add Intel Merrifield pin controller support 2016-06-29 09:59:35 +02:00
pinctrl-baytrail.c pinctrl: baytrail: Rectify debounce support (part 2) 2017-06-17 06:41:53 +02:00
pinctrl-broxton.c pinctrl: broxton: Use correct PADCFGLOCK offset 2017-02-01 08:33:12 +01:00
pinctrl-cherryview.c pinctrl: cherryview: Prevent possible interrupt storm on resume 2016-11-04 22:23:04 +01:00
pinctrl-intel.c pinctrl: intel: Set pin direction properly 2017-07-05 14:40:24 +02:00
pinctrl-intel.h pinctrl: intel: fix bug of register offset calculation 2015-12-10 23:01:41 +01:00
pinctrl-merrifield.c pinctrl: intel: merrifield: Add missed check in mrfld_config_set() 2017-02-09 08:08:29 +01:00
pinctrl-sunrisepoint.c pinctrl: intel: fix bug of register offset calculation 2015-12-10 23:01:41 +01:00