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5e4f99a6b7
If the serial interface is used, the 8-bit address should be latched using
the rising edge of the WR/FSYNC signal.
This basically means that a CS change is required between the first byte
sent, and the second one.
This change splits the single-transfer transfer of 2 bytes into 2 transfers
with a single byte, and CS change in-between.
Note fixes tag is not accurate, but reflects a point beyond which there
are too many refactors to make backporting straight forward.
Fixes:
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History
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|---|---|---|
| .. | ||
| accel | ||
| adc | ||
| addac | ||
| cdc | ||
| Documentation | ||
| frequency | ||
| impedance-analyzer | ||
| meter | ||
| resolver | ||
| Kconfig | ||
| Makefile | ||
| TODO | ||