linux/drivers/cxl
peng guo c6c16fd016 cxl/core: Fix incorrect vendor debug UUID define
[ Upstream commit 8ecef8e01a ]

When user send a mbox command whose opcode is CXL_MBOX_OP_CLEAR_LOG and
the in_payload is normal vendor debug log UUID according to
the CXL specification cxl_payload_from_user_allowed() will return
false unexpectedly, Sending mbox cmd operation fails and the kernel
log will print:
Clear Log: input payload not allowed.

All CXL devices that support a debug log shall support the Vendor Debug
Log to allow the log to be accessed through a common host driver, for any
device, all versions of the CXL specification define the same value with
Log Identifier of: 5e1819d9-11a9-400c-811f-d60719403d86

Refer to CXL spec r3.1 Table 8-71

Fix the definition value of DEFINE_CXL_VENDOR_DEBUG_UUID to match the
CXL specification.

Fixes: 472b1ce6e9 ("cxl/mem: Enable commands via CEL")
Signed-off-by: peng guo <engguopeng@buaa.edu.cn>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240710023112.8063-1-engguopeng@buaa.edu.cn
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2024-09-18 19:23:04 +02:00
..
core cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window 2024-03-01 13:26:31 +01:00
acpi.c cxl: Unify debug messages when calling devm_cxl_add_port() 2023-11-28 17:07:17 +00:00
cxl.h tools/testing/cxl: Define a fixed volatile configuration to parse 2023-11-28 17:07:17 +00:00
cxlmem.h cxl/core: Fix incorrect vendor debug UUID define 2024-09-18 19:23:04 +02:00
cxlpci.h cxl: Wait Memory_Info_Valid before access memory related info 2023-05-30 14:03:32 +01:00
Kconfig cxl/region: Allocate HPA capacity to regions 2022-07-25 12:18:06 -07:00
Makefile PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
mem.c cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem 2023-11-28 17:07:17 +00:00
pci.c cxl/pci: Create PCI DOE mailbox's for memory devices 2022-07-19 15:38:04 -07:00
pmem.c cxl/pmem: Fix nvdimm registration races 2023-03-10 09:34:20 +01:00
port.c cxl/port: Read CDAT table 2022-07-19 15:38:05 -07:00