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Dan Carpenter 769698a45f cxl/pci: fix error code in __cxl_hdm_decode_init() ... When commit 0cab687205 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window") was backported, this chunk moved from the cxl_hdm_decode_init() function which returns negative error codes to the __cxl_hdm_decode_init() function which returns false on error. So the error code needs to be modified from -ENXIO to false. This issue only exits in the 6.1.y kernels. In later kernels negative error codes are correct and the driver didn't exist in earlier kernels. Fixes: 0312171289 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		History 2024-11-22 15:37:32 +01:00
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core	cxl/pci: fix error code in __cxl_hdm_decode_init()	2024-11-22 15:37:32 +01:00
acpi.c	cxl/acpi: Move rescan to the workqueue	2024-11-08 16:26:46 +01:00
cxl.h	cxl/acpi: Move rescan to the workqueue	2024-11-08 16:26:46 +01:00
cxlmem.h	cxl/core: Fix incorrect vendor debug UUID define	2024-09-18 19:23:04 +02:00
cxlpci.h	cxl: Wait Memory_Info_Valid before access memory related info	2023-05-30 14:03:32 +01:00
Kconfig	cxl/region: Allocate HPA capacity to regions	2022-07-25 12:18:06 -07:00
Makefile	PM: CXL: Disable suspend	2022-04-22 16:09:42 -07:00
mem.c	cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem	2023-11-28 17:07:17 +00:00
pci.c	cxl/pci: Create PCI DOE mailbox's for memory devices	2022-07-19 15:38:04 -07:00
pmem.c	cxl/pmem: Fix nvdimm registration races	2023-03-10 09:34:20 +01:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00