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Add a test where a small and a large transfer in a message hit the same cache line. This test currently fails on spi-s3c64xx on in DMA mode since it ends up mixing DMA and PIO without proper cache maintenance. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220916113951.228398-2-vincent.whitchurch@axis.com Signed-off-by: Mark Brown <broonie@kernel.org>
1111 lines
27 KiB
1111 lines
27 KiB