linux/drivers/iommu/intel
Jacob Pan 2bed9455db iommu/vt-d: Fix PASID directory pointer coherency
commit 194b3348bd upstream.

On platforms that do not support IOMMU Extended capability bit 0
Page-walk Coherency, CPU caches are not snooped when IOMMU is accessing
any translation structures. IOMMU access goes only directly to
memory. Intel IOMMU code was missing a flush for the PASID table
directory that resulted in the unrecoverable fault as shown below.

This patch adds clflush calls whenever allocating and updating
a PASID table directory to ensure cache coherency.

On the reverse direction, there's no need to clflush the PASID directory
pointer when we deactivate a context entry in that IOMMU hardware will
not see the old PASID directory pointer after we clear the context entry.
PASID directory entries are also never freed once allocated.

 DMAR: DRHD: handling fault status reg 3
 DMAR: [DMA Read NO_PASID] Request device [00:0d.2] fault addr 0x1026a4000
       [fault reason 0x51] SM: Present bit in Directory Entry is clear
 DMAR: Dump dmar1 table entries for IOVA 0x1026a4000
 DMAR: scalable mode root entry: hi 0x0000000102448001, low 0x0000000101b3e001
 DMAR: context entry: hi 0x0000000000000000, low 0x0000000101b4d401
 DMAR: pasid dir entry: 0x0000000101b4e001
 DMAR: pasid table entry[0]: 0x0000000000000109
 DMAR: pasid table entry[1]: 0x0000000000000001
 DMAR: pasid table entry[2]: 0x0000000000000000
 DMAR: pasid table entry[3]: 0x0000000000000000
 DMAR: pasid table entry[4]: 0x0000000000000000
 DMAR: pasid table entry[5]: 0x0000000000000000
 DMAR: pasid table entry[6]: 0x0000000000000000
 DMAR: pasid table entry[7]: 0x0000000000000000
 DMAR: PTE not present at level 4

Cc: <stable@vger.kernel.org>
Fixes: 0bbeb01a4f ("iommu/vt-d: Manage scalalble mode PASID tables")
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reported-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Link: https://lore.kernel.org/r/20230209212843.1788125-1-jacob.jun.pan@linux.intel.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
History 2023-03-10 09:34:32 +01:00
..
cap_audit.c iommu/vt-d: Rename cap_5lp_support to cap_fl5lp_support 2022-09-26 15:52:25 +02:00
cap_audit.h iommu/vt-d: Check FL and SL capability sanity in scalable mode 2021-10-18 12:31:48 +02:00
debugfs.c iommu/vt-d: Replace spin_lock_irqsave() with spin_lock() 2022-07-15 10:21:36 +02:00
dmar.c iommu/vt-d: Fix PCI device refcount leak in dmar_dev_scope_init() 2022-12-02 11:45:33 +01:00
iommu.c iommu/vt-d: Avoid superfluous IOTLB tracking in lazy mode 2023-03-10 09:34:31 +01:00
iommu.h iommu/vt-d: Add a fix for devices need extra dtlb flush 2022-12-02 11:45:31 +01:00
irq_remapping.c iommu/vt-d: Avoid unnecessary global IRTE cache invalidation 2022-09-26 15:52:26 +02:00
Kconfig Merge branches 'apple/dart', 'arm/mediatek', 'arm/omap', 'arm/smmu', 'virtio', 'x86/vt-d', 'x86/amd' and 'core' into next 2022-09-26 15:52:31 +02:00
Makefile iommu/vt-d: Add common code for dmar latency performance monitors 2021-06-10 09:06:13 +02:00
pasid.c iommu/vt-d: Fix PASID directory pointer coherency 2023-03-10 09:34:32 +01:00
pasid.h iommu/vt-d: Remove clearing translation data in disable_dmar_iommu() 2022-07-15 10:21:34 +02:00
perf.c iommu/vt-d: Move include/linux/intel-iommu.h under iommu 2022-07-15 10:21:31 +02:00
perf.h iommu/vt-d: Add common code for dmar latency performance monitors 2021-06-10 09:06:13 +02:00
svm.c iommu/vt-d: Fix PCI device refcount leak in prq_event_thread() 2022-12-02 11:45:32 +01:00
trace.c iommu/vt-d: Move trace/events/intel_iommu.h under iommu 2022-07-15 10:21:28 +02:00
trace.h iommu/vt-d: Move include/linux/intel-iommu.h under iommu 2022-07-15 10:21:31 +02:00