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linux/arch/riscv/include
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Sergey Matyukevich eed0dc9c42 Revert "riscv: mm: notify remote harts about mmu cache updates" 
commit e921050022 upstream.

This reverts the remaining bits of commit 4bd1d80efb ("riscv: mm:
notify remote harts harts about mmu cache updates").

According to bug reports, suggested approach to fix stale TLB entries
is not sufficient. It needs to be replaced by a more robust solution.

Fixes: 4bd1d80efb ("riscv: mm: notify remote harts about mmu cache updates")
Reported-by: Zong Li <zong.li@sifive.com>
Reported-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Cc: stable@vger.kernel.org
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20230226150137.1919750-2-geomatsi@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
History 2023-03-22 13:34:00 +01:00
..
asm Revert "riscv: mm: notify remote harts about mmu cache updates" 2023-03-22 13:34:00 +01:00
uapi/asm RISC-V Patches for the 6.1 Merge Window, Part 2 2022-10-14 11:21:11 -07:00