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Xu Lu d2bd51954a riscv: mm: Fix the out of bound issue of vmemmap address 
[ Upstream commit f754f27e98 ]

In sparse vmemmap model, the virtual address of vmemmap is calculated as:
((struct page *)VMEMMAP_START - (phys_ram_base >> PAGE_SHIFT)).
And the struct page's va can be calculated with an offset:
(vmemmap + (pfn)).

However, when initializing struct pages, kernel actually starts from the
first page from the same section that phys_ram_base belongs to. If the
first page's physical address is not (phys_ram_base >> PAGE_SHIFT), then
we get an va below VMEMMAP_START when calculating va for it's struct page.

For example, if phys_ram_base starts from 0x82000000 with pfn 0x82000, the
first page in the same section is actually pfn 0x80000. During
init_unavailable_range(), we will initialize struct page for pfn 0x80000
with virtual address ((struct page *)VMEMMAP_START - 0x2000), which is
below VMEMMAP_START as well as PCI_IO_END.

This commit fixes this bug by introducing a new variable
'vmemmap_start_pfn' which is aligned with memory section size and using
it to calculate vmemmap address instead of phys_ram_base.

Fixes: a11dd49dcb ("riscv: Sparse-Memory/vmemmap out-of-bounds fix")
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20241209122617.53341-1-luxu.kernel@bytedance.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2025-01-17 13:40:44 +01:00
..
cache-ops.c riscv: split cache ops out of dma-noncoherent.c 2023-11-07 09:37:42 -08:00
cacheflush.c riscv: Disable preemption while handling PR_RISCV_CTX_SW_FENCEI_OFF 2024-09-10 20:38:46 -07:00
context.c Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements" 2024-04-30 10:35:48 -07:00
dma-noncoherent.c dma-mapping: Simplify arch_setup_dma_ops() 2024-04-26 12:07:28 +02:00
extable.c riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW 2024-01-09 20:18:20 -08:00
fault.c riscv/mm: Add handling for VM_FAULT_SIGSEGV in mm_fault_error() 2024-08-01 07:15:27 -07:00
hugetlbpage.c mm: provide mm_struct and address to huge_ptep_get() 2024-07-12 15:52:15 -07:00
init.c riscv: mm: Fix the out of bound issue of vmemmap address 2025-01-17 13:40:44 +01:00
kasan_init.c percpu: 2024-01-18 15:01:28 -08:00
Makefile riscv: mm: Combine the SMP and UP TLB flush code 2024-04-29 10:49:29 -07:00
pageattr.c riscv: rewrite __kernel_map_pages() to fix sleeping in invalid context 2024-05-22 09:15:09 -07:00
pgtable.c riscv: Stop emitting preventive sfence.vma for new userspace mappings with Svvptc 2024-09-15 00:11:05 -07:00
physaddr.c riscv: Use PUD/P4D/PGD pages for the linear mapping 2023-04-18 20:43:04 -07:00
pmem.c RISC-V: capitalise CMO op macros 2023-11-05 09:11:23 -08:00
ptdump.c riscv: mm: Take memory hotplug read-lock during kernel page table dump 2024-06-26 08:42:43 -07:00
tlbflush.c RISC-V Patches for the 6.10 Merge Window, Part 1 2024-05-22 09:56:00 -07:00