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linux/arch/riscv/mm
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Andy Chiu 1346d12e46 riscv: add a data fence for CMODX in the kernel mode 
[ Upstream commit ca358692de ]

RISC-V spec explicitly calls out that a local fence.i is not enough for
the code modification to be visble from a remote hart. In fact, it
states:

To make a store to instruction memory visible to all RISC-V harts, the
writing hart also has to execute a data FENCE before requesting that all
remote RISC-V harts execute a FENCE.I.

Although current riscv drivers for IPI use ordered MMIO when sending IPIs
in order to synchronize the action between previous csd writes, riscv
does not restrict itself to any particular flavor of IPI. Any driver or
firmware implementation that does not order data writes before the IPI
may pose a risk for code-modifying race.

Thus, add a fence here to order data writes before making the IPI.

Signed-off-by: Andy Chiu <andybnac@gmail.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20250407180838.42877-8-andybnac@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2025-07-06 11:01:35 +02:00
..
cache-ops.c riscv: split cache ops out of dma-noncoherent.c 2023-11-07 09:37:42 -08:00
cacheflush.c riscv: add a data fence for CMODX in the kernel mode 2025-07-06 11:01:35 +02:00
context.c Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements" 2024-04-30 10:35:48 -07:00
dma-noncoherent.c dma-mapping: Simplify arch_setup_dma_ops() 2024-04-26 12:07:28 +02:00
extable.c riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW 2024-01-09 20:18:20 -08:00
fault.c riscv/mm: Add handling for VM_FAULT_SIGSEGV in mm_fault_error() 2024-08-01 07:15:27 -07:00
hugetlbpage.c riscv: Fix hugetlb retrieval of number of ptes in case of !present pte 2025-04-10 14:39:32 +02:00
init.c riscv: mm: Fix the out of bound issue of vmemmap address 2025-01-17 13:40:44 +01:00
kasan_init.c percpu: 2024-01-18 15:01:28 -08:00
Makefile riscv: mm: Combine the SMP and UP TLB flush code 2024-04-29 10:49:29 -07:00
pageattr.c riscv: rewrite __kernel_map_pages() to fix sleeping in invalid context 2024-05-22 09:15:09 -07:00
pgtable.c riscv: Stop emitting preventive sfence.vma for new userspace mappings with Svvptc 2024-09-15 00:11:05 -07:00
physaddr.c riscv: Use PUD/P4D/PGD pages for the linear mapping 2023-04-18 20:43:04 -07:00
pmem.c RISC-V: capitalise CMO op macros 2023-11-05 09:11:23 -08:00
ptdump.c riscv: mm: Take memory hotplug read-lock during kernel page table dump 2024-06-26 08:42:43 -07:00
tlbflush.c riscv: Call secondary mmu notifier when flushing the tlb 2025-05-29 11:02:14 +02:00