linux

mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ synced 2026-11-13 07:31:07 +00:00

Radim Krčmář fecd903917 riscv: use lw when reading int cpu in asm_per_cpu commit `f4ea67a722` upstream. REG_L is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide. The struct currently has a hole after cpu, so little endian accesses seemed fine. Fixes: `be97d0db5f` ("riscv: VMAP_STACK overflow detection thread-safe") Cc: stable@vger.kernel.org Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250725165410.2896641-5-rkrcmar@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>	History 2025-09-09 18:58:26 +02:00
..
asm	riscv: use lw when reading int cpu in asm_per_cpu	2025-09-09 18:58:26 +02:00
uapi/asm	RISC-V: hwprobe: Add SCALAR to misaligned perf defines	2024-08-14 13:13:24 -07:00

Radim Krčmář fecd903917 riscv: use lw when reading int cpu in asm_per_cpu

commit f4ea67a722 upstream.

REG_L is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide.
The struct currently has a hole after cpu, so little endian accesses
seemed fine.

Fixes: be97d0db5f ("riscv: VMAP_STACK overflow detection thread-safe")
Cc: stable@vger.kernel.org
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
Link: https://lore.kernel.org/r/20250725165410.2896641-5-rkrcmar@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

History

2025-09-09 18:58:26 +02:00

asm riscv: use lw when reading int cpu in asm_per_cpu 2025-09-09 18:58:26 +02:00

uapi/asm RISC-V: hwprobe: Add SCALAR to misaligned perf defines 2024-08-14 13:13:24 -07:00