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linux/drivers/clk/xilinx
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Shubhrajyoti Datta a1f310511c clk: clocking-wizard: Fix output clock register offset for Versal platforms 
[ Upstream commit 7c2e86f7b5 ]

The output clock register offset used in clk_wzrd_register_output_clocks
was incorrectly referencing 0x3C instead of 0x38, which caused
misconfiguration of output dividers on Versal platforms.

Correcting the off-by-one error ensures proper configuration of output
clocks.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2025-11-13 15:34:34 -05:00
..
clk-xlnx-clock-wizard.c clk: clocking-wizard: Fix output clock register offset for Versal platforms 2025-11-13 15:34:34 -05:00
Kconfig clk: xilinx: Drop duplicate depends on COMMON_CLK 2022-10-17 15:30:00 -07:00
Makefile clk: clocking-wizard: Move clocking-wizard out 2022-08-22 19:07:10 -07:00
xlnx_vcu.c clk: xilinx: vcu: unregister pll_post only if registered correctly 2025-08-15 12:13:50 +02:00