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clk-cpu.c
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clk: Fix typos
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2025-07-26 23:49:18 -07:00 |
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clk-ddr.c
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clk: rockchip: ddr: convert from round_rate() to determine_rate()
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2025-09-08 09:41:30 -04:00 |
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clk-gate-grf.c
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clk: rockchip: rename gate-grf clk file
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2025-05-13 20:30:15 +02:00 |
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clk-half-divider.c
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clk: rockchip: half-divider: convert from round_rate() to determine_rate()
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2025-09-08 09:41:25 -04:00 |
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clk-inverter.c
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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
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2019-05-30 11:26:37 -07:00 |
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clk-mmc-phase.c
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clk: Fix typos
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2025-07-26 23:49:18 -07:00 |
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clk-muxgrf.c
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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282
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2019-06-05 17:36:37 +02:00 |
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clk-pll.c
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clk: rockchip: pll: convert from round_rate() to determine_rate()
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2025-09-08 09:41:30 -04:00 |
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clk-px30.c
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clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage
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2024-08-28 21:25:49 +02:00 |
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clk-rk3036.c
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clk: rockchip: rk3036: mark ddrphy as critical
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2025-05-08 20:29:02 +02:00 |
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clk-rk3128.c
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clk: rockchip: rk3128: Add HCLK_SFC
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2024-06-23 22:10:43 +02:00 |
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clk-rk3188.c
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clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066
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2025-02-26 17:52:48 +01:00 |
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clk-rk3228.c
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clk: rockchip: rk3228: Drop CLK_NR_CLKS usage
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2024-08-28 21:25:49 +02:00 |
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clk-rk3288.c
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clk: rockchip: introduce auxiliary GRFs
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2025-05-05 22:39:24 +02:00 |
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clk-rk3308.c
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clk: rockchip: rk3308: Drop CLK_NR_CLKS usage
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2024-08-28 21:25:50 +02:00 |
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clk-rk3328.c
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clk: rockchip: introduce auxiliary GRFs
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2025-05-05 22:39:24 +02:00 |
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clk-rk3368.c
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clk: rockchip: rk3368: use clock ids for SCLK_MIPIDSI_24M
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2025-09-03 14:17:54 +02:00 |
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clk-rk3399.c
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clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage
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2024-08-28 21:25:50 +02:00 |
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clk-rk3528.c
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clk: rockchip: rk3528: add slab.h header include
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2025-05-15 14:49:05 +02:00 |
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clk-rk3562.c
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clk: rockchip: Add clock controller for the RK3562
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2025-03-02 17:51:51 +01:00 |
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clk-rk3568.c
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clk: rockchip: rk3568: Add PLL rate for 132MHz
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2025-07-10 13:47:36 +02:00 |
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clk-rk3576.c
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I've recently moved computers (among other things) so I'm sending this from a
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2025-05-30 09:15:40 -07:00 |
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clk-rk3588.c
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clk: rockchip: rk3588: Add PLL rate for 1500 MHz
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2025-04-10 14:28:14 +02:00 |
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clk-rv1108.c
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clk: rockchip: support more core div setting
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2021-03-21 11:10:58 +01:00 |
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clk-rv1126.c
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clk: rockchip: introduce auxiliary GRFs
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2025-05-05 22:39:24 +02:00 |
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clk.c
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clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()
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2026-02-26 14:59:30 -08:00 |
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clk.h
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clk: Fix typos
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2025-07-26 23:49:18 -07:00 |
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gate-link.c
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clk: rockchip: implement linked gate clock support
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2025-01-09 16:19:21 +01:00 |
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Kconfig
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clk: rockchip: Add clock controller for the RK3562
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2025-03-02 17:51:51 +01:00 |
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Makefile
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clk: rockchip: rename gate-grf clk file
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2025-05-13 20:30:15 +02:00 |
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rst-rk3528.c
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clk: rockchip: rk3528: Add reset lookup table
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2025-02-27 20:08:25 +01:00 |
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rst-rk3562.c
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clk: rockchip: Add clock controller for the RK3562
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2025-03-02 17:51:51 +01:00 |
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rst-rk3576.c
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clk: rockchip: Add clock controller for the RK3576
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2024-08-29 11:13:33 +02:00 |
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rst-rk3588.c
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clk: rockchip: rk3588: Add reset line for HDMI Receiver
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2024-04-10 07:10:40 +02:00 |
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softrst.c
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clk: rockchip: add lookup table support
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2022-11-14 15:35:07 +01:00 |
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