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linux/drivers/phy/rockchip
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Cristian Ciocaltea 05ce13d782 phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output 
[ Upstream commit f2daf0c67a ]

Attempting to make use of a 1080p@120Hz display mode with 10 bpc RGB on
my Acer XV275K P3 monitor results in a blank image.  A similar behavior
has been reported on Philips 279M1RV.

The faulty modeline is created by drm_gtf_mode_complex() based on the
following EDID entry from the Standard Timings block:

  GTF:  1920x1080  119.999987 Hz  16:9    138.840 kHz    368.759000 MHz

It's worth noting the computed pixel clock ends up being slightly higher
at 368.881000 MHz.  Nevertheless, this seems to work consistently fine
with 8 bpc RGB.

After switching to 10 bpc, the TMDS character rate expected for the mode
increases to 461.101250 MHz, as per drm_hdmi_compute_mode_clock().

Since there is no entry for this rate in the ropll_tmds_cfg table, the
necessary HDMI PLL configuration parameters are calculated dynamically
by rk_hdptx_phy_clk_pll_calc().  However, the resulting output rate is
not quite a perfect match, i.e. 461.100000 MHz.  That proved to be the
actual root cause of the problem.

Add a new entry to the TMDS configuration table and provide the
necessary frequency division coefficients for the PHY PLL to generate
the expected 461.101250 MHz output.

Fixes: 9d0ec51d7c ("phy: rockchip: samsung-hdptx: Add high color depth management")
Tested-by: Derek Foreman <derek.foreman@collabora.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20251221-phy-hdptx-pll-fix-v2-1-ae4abf7f75a1@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2026-02-26 14:59:32 -08:00
..
Kconfig phy-for-6.15 2025-04-01 12:47:11 -07:00
Makefile phy: rockchip: Add Samsung MIPI D-/C-PHY driver 2025-03-16 22:10:46 +05:30
phy-rockchip-dp.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 178 2019-05-30 11:29:19 -07:00
phy-rockchip-dphy-rx0.c phy: Explicitly include correct DT includes 2023-07-17 11:52:56 +05:30
phy-rockchip-emmc.c phy: rockchip-emmc: switch to FIELD_PREP_WM16 macro 2025-09-02 20:06:46 -04:00
phy-rockchip-inno-csidphy.c phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant 2025-09-11 10:02:13 +05:30
phy-rockchip-inno-dsidphy.c phy: Switch back to struct platform_driver::remove() 2024-10-17 20:33:03 +05:30
phy-rockchip-inno-hdmi.c phy: Switch back to struct platform_driver::remove() 2024-10-17 20:33:03 +05:30
phy-rockchip-inno-usb2.c phy: rockchip: inno-usb2: fix disconnection in gadget mode 2026-01-23 11:21:26 +01:00
phy-rockchip-naneng-combphy.c phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562 2025-12-18 14:03:08 +01:00
phy-rockchip-pcie.c phy: rockchip-pcie: switch to FIELD_PREP_WM16 macro 2025-09-22 15:52:44 -04:00
phy-rockchip-samsung-dcphy.c phy: rockchip-samsung-dcphy: switch to FIELD_PREP_WM16 macro 2025-09-02 20:06:47 -04:00
phy-rockchip-samsung-hdptx.c phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output 2026-02-26 14:59:32 -08:00
phy-rockchip-snps-pcie3.c phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode 2024-04-13 11:36:15 +05:30
phy-rockchip-typec.c phy: rockchip: phy-rockchip-typec: Fix Copyright description 2024-12-25 01:17:33 +05:30
phy-rockchip-usb.c phy: rockchip-usb: switch to FIELD_PREP_WM16 macro 2025-09-02 20:06:47 -04:00
phy-rockchip-usbdp.c phy: rockchip: usbdp: Remove redundant ternary operators 2025-09-01 18:13:54 +05:30